DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 6/10/2026, with respect to the 103 rejection of claims 1-3, 9-11, 17-19, and 25-27 in view of Shimzu and Myung have been fully considered and are persuasive. The corresponding rejection has been withdrawn.
Applicant's arguments with respect to the 102 and 103 rejections in view of Li et al have been fully considered but they are not persuasive.
Applicant argues that the term MSB in Li refers to a more significant bit rather than a most significant bit, and that writing the codeword in the row direction where a column pair is a modulation symbol results in assigning two sequential bits to the same modulation symbol.
The Examiner asserts that the MSB of Li (referred to as “more significant bit”) takes on the accepted well-known meaning in the art which is the same identical meaning of the term as Applicant’s specification. It can be clearly seen that “more significant bit” is relative to the “less significant bit” and that Fig. 2 explicitly shows bits of the first row as the most significant bits.
Regarding Applicant’s second argument, The Examiner notes that Li still meets the claimed limitations because assigning two sequential bits to the same modulation symbol still meets the claim language “wherein the most significant bit available across two or more modulation symbols is a first available bit with a lowest symbol index and a lowest bit index within the two of more modulation symbols”. Assuming that the lowest symbol index is S and a lowest bit index is B, a first available bit is assigned to symbol index S and bit index B of the first column pair. A next available bit is assigned to symbol index S (because S is still the lowest symbol index that can be used) and bit index B+1 for the second column pair of Li. Alternatively, one of ordinary skill in the art could have assigned different symbol indexes to each component such that the first component of the column pair has symbol S, and the second component of the column pair has symbol S+1. Any of these arrangements would not have changed the principle of operation or teachings of Li and would have met the claim language as explained above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 8-11, 13, 16-19, 21, 24-27, and 29 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Li et al (US Pat. Pub. 2009/0180495; hereinafter referred to as Li).
As per claims 1, 9, 17, 25: Li teaches a method, apparatus, and non-transitory computer-readable medium for wireless communications, comprising:
a memory in communication with a processor (Fig. 1) configured for:
encoding a code block using a Low Density Parity Check (LDPC) code (Fig. 1, 109) to generate a stream of encoded bits including systematic bits and parity bits arranged with the systematic bits followed by the parity bits (paragraph 16, Equation 4 and paragraph 49, Equation 6);
mapping each bit in the stream of encoded bits sequentially to a most significant bit (Fig. 2, systematic bits are mapped starting with MSBs; paragraph 62) available across two or more modulation symbols (Fig. 2, each column pair is a modulation symbol as explained in paragraph 54; see also paragraph 50); and
transmitting the two or more modulation symbols (Fig. 1, 101 and 106).
As per claims 2, 10, 18, 26: Li further teaches the method, apparatus, and medium above, wherein systematic bits are located in a most significant bit of each of the two or more modulation symbols (Fig. 2, systematic bits in MSB positions).
As per claims 3, 11, 19, 27: Li further teaches the method, apparatus, and medium above, wherein parity bits are located in a least significant bit of each of the two or more modulation symbols (Fig. 2, parity bits in LSB positions).
As per claims 5, 13, 21, 29: Li further teaches the method, apparatus, and medium above, wherein mapping each bit in the stream of encoded bits sequentially to a most significant bit available across two or more modulation symbols comprises assigning a location to each encoded bit based on a formula (paragraphs 59-61).
As per claims 8, 16, 24: Li teaches the method, apparatus, and medium above, wherein mapping each bit in the stream of encoded bits sequentially to a most significant bit available across two or more modulation symbols comprises:
selecting a first symbol of the two or more modulation symbols that has a bit location that is in a most significant position that is available among the two or more modulation symbols (Fig. 2, first row of the first column; paragraph 54), and
selecting a location of a next encoded bit a most significant bit location that is available within the selected symbol (Fig. 2, first row of the second column; paragraph 54).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, 7, 12, 15, 20, 23, and 28 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Li in view of Jeong et al (US Pat. Pub. 2012/0051460; hereinafter referred to as Jeong).
As per claims 4, 12, 20, and 28: Li teaches the apparatus and method above. Not explicitly disclosed is wherein the encoded bits are arranged with the systematic bits followed by the parity bits based on a mapping table. However, Jeong in an analogous art teaches a bit mapper (Fig. 5, 515) that arranges bits of an encoded codeword based on a mapping table (paragraph 51).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to use the transmitter of Jeong in the system of Li. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it could have equivalently been used to perform the transmission functions disclosed by Li.
As per claims 7, 15, 23: Li teaches the apparatus and method above. Not explicitly disclosed is wherein mapping each bit in the stream of encoded bits sequentially to a most significant bit available across two or more modulation symbols is performed in a bit level interleaving operation. However, Jeong in an analogous art teaches a transmitter comprising a bit interleaver (Fig. 5, 513; Fig. 6, 611).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to perform the mapping of Li in a bit level interleaving operation. This modification would have been obvious for one of ordinary skill in the art at the time of filing because doing so would have minimized error rate in modulating the codeword (paragraph 76).
Claims 6, 14, 22, 30 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Li in view of Yano et al (US Pat. Pub. 2009/0290544; hereinafter referred to as Yano).
As per claims 6, 14, 22, 30: Li teaches the apparatus and method above. Not explicitly disclosed is wherein the systematic bits and the parity bits are arranged in an order based on an encoding scheme of the LDPC code. However, Yano in an analogous art teaches an irregular encoding LDPC scheme arranged in an order based on column degree (paragraph 50).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to arrange the bits of Li based on an encoding scheme of the LDPC code. This modification would have been obvious for one of ordinary skill in the art at the time of filing because performance gains increase with column weights, as taught by Li in paragraph 76.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE N NGUYEN whose telephone number is (571)272-7214. The examiner can normally be reached M-F 9-5.
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/STEVE N NGUYEN/Primary Examiner, Art Unit 2111
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