DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received November
20, 2024 for application number 18/953997. The Office hereby acknowledges receipt of the
following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, and
Claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 14 objected to because of the following informalities: "Transition (emphasis added). Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under
35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Severino et al. (US 10,908,667 B2) in view of Arbel et al. (US 2023/0376248 A1).
Regarding Claim 1, Severino teaches:
“A power management circuit (PMC) configured to: determine, based on a set of one or more performance state requests received from one or more requestors within the computer system” ([C10:L50-57] During normal operation, the Power Processing Unit (PPU) 100 (i.e. requestor)(the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM) can signal to the Power Conversion and Storage Module (PCSM) 110 (i.e. PMC) when it decides that it wishes to change the power state (i.e. performance state requests) of the power domain being controlled by it. In particular, it can assert a request signal over path 120));
“A target performance state for the computer system having component performance states that are specified externally to the PMC as being available to the one or more requestors” ([C10:L56-62] The PCSM 110 (i.e. the PMC) can then be responsive to the asserted request signal on path 120 (i.e. available to the requestor), to undertake the necessary power switching control required to implement the target power state indicated by the pstate signal on path 125, and once those steps have been taken, can assert a paccept signal over path 130 (i.e. external to the PMC) back to the PPU 100 (i.e. the requestor) (the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM));
“Permit a transition to an internal performance state for the computer system that is defined internally within the PMC” ([C11:L59-62] FIG. 5 is a similar flow diagram to FIG. 4, but illustrates the sequence of steps when the PPU decides that the power state of the domain (i.e. defined internally within the PMC) should be transitioned to a less power saving state (i.e. permit a transition to an internal performance state));
“Wherein the internal performance state has at least one component performance state not specified externally to the PMC as being available to be requested by the one or more requestors” ([C8:L28-35] It can hence be seen that the PPU (i.e. requestor) components 17, 24 are used to control the functional behavior of components within the controlled power domain to ensure that appropriate actions are taken by those components taking into account the transition in the power state that is being implemented (i.e. the internal performance state has at least one external performance state not specified externally to the PMC, as functional behavior of components are controlled but the behavior of the components are not part of the externally available requests). In contrast, the PCSM (i.e. external to the PMC) components 22, 26 are used to handle the actual switching of the power supply required when transitioning between different power states);
Severino does not teach:
“An apparatus, comprising a computer system: the computer system including: a plurality of agent circuits within a first power domain”
“An apparatus, comprising: a computer system implemented on one or more co-packaged integrated circuit dies”
“One or more memory interface circuits within a second power domain”
“Wherein agent circuits of the plurality of agent circuits are configured to access the one or more memory interface circuits over a boundary between the first power domain and the second power domain”
However, in the analogous art of a system-on-chip (SoC) that includes a memory subsystem, Arbel does teach:
“An apparatus, comprising a computer system: the computer system including: a plurality of agent circuits within a first power domain” ([0024] Various modules of the IC 100 are in different power domains. For example, the Processing System (PS) 102 ([0019] The PS 102 can be or include one or more processor cores. For example, the PS 102 can include a number of ARM-based embedded processor cores (i.e. a plurality of agent circuits) is in a first power domain 202)
“An apparatus, comprising: a computer system implemented on one or more co-packaged integrated circuit dies” ([0018] FIG. 1 is a block diagram of an integrated circuit (IC) 100; The IC 100 may be a system-on-chip (SoC) and may be implemented on a single die. The IC 100 includes a processing system (PS) 102);
“One or more memory interface circuits within a second power domain” ([0016] the memory subsystem includes one or more memory controllers (i.e. memory interface circuits) that are in a power domain separate and independent from power domains of master modules (i.e. within a second power domain));
“Wherein agent circuits of the plurality of agent circuits are configured to access the one or more memory interface circuits over a boundary between the first power domain and the second power domain” ([0033] At block 304, memory is accessed by at least one of the master modules, via the memory controller (i.e. memory interface circuits) of the IC, irrespective of the power mode of each of the other master modules in power domain(s) separate from the power domain of the at least one master modules accessing the memory (i.e. a boundary between the first power domain and second power domain); [0006] The first memory controller is in a power domain separate from each respective power domain of the plurality of master circuits).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino and Arbel before him, before the effective filing date of the claimed invention , to incorporate Arbel’s operation of a memory controller independently of master circuits within the integrated circuit in Severino’s integrated circuit for managing power domains to offer an alternative to multi-chip designs with integration of components into a single device to increase overall speed while decreasing size (Arbel [0003]).
Regarding Claim 4, Severino in view of Arbel teaches “The apparatus of claim 1”. Severino further discloses:
“Wherein the set of one or more performance state requests specify one or more of the following parameters: a bandwidth request, a latency request, a real-time request, a particular performance state for the first power domain, a particular performance state for the second power domain” ([C1:L59-64] whilst a current power state of the first power domain is any one of at least two of the plurality of power states, the second power domain is allowed to be placed (by the PPU 100 (i.e. the requestor)) in a power saving state (i.e. a particular performance state for the second power domain) where the power control means loses knowledge of the current power state of the first power domain);
Regarding Claim 5, Severino in view of Arbel teaches “The apparatus of claim 1”. Severino further discloses:
“Wherein the one or more requestors include one or more of the plurality of agent circuits and one or more software entities” (C8:L43-47] In the example shown in FIG. 1, a system control processor (SCP) 28 is provided. This is an independent processor (i.e. agent circuit) which can be used to manage the PPUs 17, 24 (i.e. the one or more requestors). In particular, via the programming interfaces 65, 70, the SCP can be used to program the PPUs 17, 24 as desired; [C10:L8-11] The integrated circuit of FIG. 2 is essentially the same as that shown in FIG. 1, but instead of a dedicated SCP 28, software executing on the cluster 12 (i.e. software entity) is used to program the PPUs 17, 24 via the paths 85, 90, 95);
“Wherein the plurality of agent circuits includes one or more of the following types of agent circuits: processor circuits, memory controller circuits, I/O agent circuits, graphics processing circuits” ([C8:L43-45] In the example shown in FIG. 1, a system control processor (SCP) 28 (i.e. processor circuit) is provided. This is an independent processor which can be used to manage the PPUs 17, 24).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Severino in view of Arbel, and further in view of Allen-Ware et al. (US 2014/0149763 A1).
Regarding Claim 2, Severino in view of Arbel teach “The apparatus of claim 1”.
Severino in view of Arbel does not teach:
“Wherein the internal performance state and the target performance state specify different operating values for a particular circuit within the computer system”
However, in the analogous art of computing system voltage control methods Allen-Ware does teach “Wherein the internal performance state and the target performance state specify different operating values for a particular circuit within the computer system” ([0027] At stage D, the validator 130 reads each register value and determines what performance state value (i.e. internal performance state) to send to the voltage controller 112 (i.e. a particular circuit within the computer system); The target performance state is the requested performance state with the performance state voltage offset value applied to it (i.e. different operating values for each performance state)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, and Allen-Ware before him, before the effective filing date of the claimed invention, to incorporate Allen-Ware’s reading of a register value to determine a performance state value into the system disclosed by Severino and Arbel to reduce power consumption associated with data centers ([0003] Allen-Ware).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Severino in view of Arbel, Allen-Ware, and further in view of Garg et al. (US 2022/0100247 A1), as listed in the IDS dated 11/20/24.
Regarding Claim 3, the combination of Severino, Arbel, and Allen-Ware teaches “The apparatus of claim 2”.
Allen-Ware further discloses:
“Wherein the target performance state is (P1, P2)” ([0036] At block 201, the performance state voltage offset value is subtracted from the requested performance state to get the target performance state. The performance states can be implemented as integer values, such that P0 (i.e. P1) is represented by 0, P1 (i.e. P2) is represented by 1, and so on).
The combination of Severino, Arbel, and Allen-Ware does not teach:
“Wherein the target performance state is (P1, P2), wherein P1 and P2 are component performance states for the first and second power domains respectively”
“Wherein component performance state P2 is also associated with a first frequency for a crossover clock signal that crosses the boundary between the first power domain and the second power domain”
“Wherein the internal performance state is (P1, P2’)”
“Wherein P2’ differs from P2 by being associated with a second, different frequency for the crossover clock signal”
However, in the analogous art of hierarchical power management (HPM) architecture Garg does disclose:
“Wherein the target performance state is (P1, P2), wherein P1 and P2 are component performance states for the first and second power domains respectively” ([0450] In an illustrative scenario according to one embodiment, some or all of P-units 4520, 4530, 4540 each receive from P-unit 4510 (i.e. components) a respective communication which specifies or otherwise indicates a power budget for a corresponding power domain (e.g., wherein a communication identifies a frequency budget to implement a corresponding power budget). For example, message 4514 indicates to P-unit 4520 (i.e. P1) a first frequency budget for a first power domain—e.g., wherein message 4516 indicates to P-unit 4530 (i.e. P2) a second frequency budget for a second power domain (i.e. component performance states for the first and second power domains respectively);
“Wherein component performance state P2 is also associated with a first frequency for a crossover clock signal that crosses the boundary between the first power domain and the second power domain” ([0451] In its capacity as a supervisee, P-units 4520 distributes the first frequency budget (i.e. component performance state P2) among a first one or more processor cores of the first power domain—e.g., wherein P-units 4530 similarly distributes the second frequency budget among a second one or more processor cores of the second power domain. (i.e. frequency change crossing over the fabric domain 4607 boundary as mentioned in [0281-0282] and Fig. 46);
“Wherein the internal performance state is (P1, P2’)” ([0448] P-unit 4510 specifies or otherwise indicates to each of P-units 4520 (i.e. P1), 4530 (e.g., via messages 4514 , 4516) a respective one or more frequency thresholds to be applied each to a corresponding core (i.e. internal performance states); [0450] Furthermore, message 4518 indicates to P-unit 4540 (i.e. P2’) a third frequency budget for a third power domain
“Wherein P2’ differs from P2 by being associated with a second, different frequency for the crossover clock signal”[0451] P-units 4530 (i.e. P2) similarly distributes the second frequency budget among a second one or more processor cores of the second power domain; [0452] In its capacity as a supervisee, P-unit 4540 (i.e. P2’) identifies a first portion of the third frequency budget (i.e. a second, different frequency), and distributes said first portion among a third one or more cores of a first sub-domain of the third power domain.
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, Allen-Ware, and Garg before him, the effective filing date of the claimed invention, to incorporate Garg’s various frequencies of component performance states into the system disclosed by Severino, Arbel, and Allen-Ware to maximize power and performance (PnP) for the system-on-chip (SoC) ([0002] Garg).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Severino in view of Arbel, Allen-Ware, Garg, and further in view of Nakamura (US 2023/0104672 A1).
Regarding Claim 6, Severino in view of Arbel teach “The apparatus of claim 1”. Allen-Ware further discloses:
“Wherein the PMC includes a transition protection circuit configured to: provide an indication of the target performance state” ([0023] FIG. 1 depicts the interactions between components of a computing system that utilizes a voltage safety verification unit (i.e. transition protection circuit); [0028] If the target performance state does not fall into the specified range, the validator 130 determines the minimum performance state possible (i.e. provide an indication of the target performance state)).
The combination of Severino, Arbel, Allen-Ware, and Garg does not teach:
“Wherein the PMC includes a transition protection circuit configured to: provide an indication of the target performance state to each of a plurality of transition table circuits that includes a first transition table circuit that specifies a particular transition permission value”
“Select, based on a current mode of the transition protection circuit, the particular transition permission value from the first transition table circuit”
“The particular transition permission value indicating that the transition to the internal performance state is permitted”
However, in the analogous art of information processing within a selected power control mode Nakamura does teach:
“A target performance state of each of a plurality of transition table circuits that includes a first transition table circuit that specifies a particular transition permission value” ([0082] a mode transition table may be stored in advance, separate from the power control table. The mode transition table is configured to include information indicative of the mode transition conditions or the mode transition parameters for each power control mode after being changed (i.e. a particular transition permission value). More specifically, SP11, T11, SP12, and T12 (i.e. target performance modes) may be included in the mode transition table; [0083] The performance control unit 217 (i.e. transition table circuit) refers to the mode transition table to identify, for each processor, the mode transition condition satisfied by the state of the processor);
“Select, based on a current mode of the transition protection circuit, the particular transition permission value from the first transition table circuit” ([0083] The performance control unit 217 refers to the mode transition table to identify, for each processor, the mode transition condition satisfied by the state of the processor, and changes the power control mode to the one pertaining to the identified mode transition condition);
“The particular transition permission value indicating that the transition to the internal performance state is permitted” ([0138] the performance control unit 217 identifies the upgrading condition to a power control mode with the highest PL1 from among the satisfied upgrading conditions (i.e. the particular transition permission value), and gives priority to a transition to the power control mode pertaining to the identified upgrading condition (i.e. indicating the transition to the internal performance state is permitted)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, Allen-Ware, Garg, and Nakamura before him, before the effective filing date of the claimed invention, to incorporate Nakamura’s transition and power control tables into the system disclosed by Severino, Arbel, Allen-Ware, and Garg to provide more advanced image processing functionality ([0003] Nakamura).
Regarding Claim 7, The combination of Severino, Arbel, Allen-Ware, and Garg teaches “The apparatus of Claim 6”.
Nakamura further discloses:
“Wherein, in response to an occurrence of a first particular state transition, the transition protection circuit is configured to enter a first mode in which the first of the plurality of transition table circuits is selected for transition checking until occurrence of a second particular state transition” ([0083] The performance control unit 217 refers to the mode transition table to identify, for each processor, the mode transition condition satisfied by the state of the processor, and changes the power control mode to the one pertaining to the identified mode transition condition; [0132] In the mode transition table, upgrading conditions are arranged in descending order of the PL1 in a power control mode after being changed, i.e., in the order of the high performance mode (P) and the balance mode (B) (i.e. first mode). Further, downgrading conditions are arranged in ascending order of the PL1 in a power control mode after being changed, i.e., in the order of the low noise mode (Q) and the balance mode (B) (i.e. second state transition). The order of these mode transition conditions corresponds to the priority of the mode transition conditions to be applied by the performance control unit 217 (i.e. transition table circuit selected for checking)).
Allen-Ware further discloses:
“At which time the transition protection circuit is configured to enter a second mode in which a second of the plurality of transition table circuits is selected for transition checking until a subsequent occurrence of the first particular state transition” ([0023] FIG. 1 depicts the interactions between components of a computing system that utilizes a voltage safety verification unit; [0064] At stage A, the hypervisor 502 (i.e. by way of both the P-state register 128 and validator 120; residing within the Voltage Safety Verification Unit) requests a performance state change, and the frequency associated with the requested performance state is written to the performance state frequency register 514. When the performance state frequency register 514 is written to the time measurement circuit 512 and the cycle counter register 516 are reset to zero. The time measurement circuit 512 calculates the amount of time that has elapsed since the time measurement circuit 512 was last reset. The cycle counter register 516 receives an indication of a cycle from an oscillator, which can take the form of an electrical pulse. Each time the cycle counter register 516 receives an indication of a cycle, the value in the cycle counter register 516 is incremented; [0065] At stage B, the current value in the time measurement circuit 512 is multiplied by the frequency of the current performance state, which is stored in the performance state frequency register 514. Stage B (i.e. a second mode) occurs in response to the performance state frequency being written to the performance state frequency register 514 in stage A. In other words, when a new value is written to the performance state frequency register 514, the current values in the performance state frequency register 514 and time measurement circuit 512 are multiplied before being reset (i.e. until a subsequent occurrence of the first particular state transition)
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Severino in view of Arbel, and further in view of Ahmad et al. (US 2014/0032947 A1).
Regarding Claim 8, Severino in view of Arbel teaches “The apparatus of claim 1”. Severino in view of Arbel does not teach:
“Wherein, to determine the target performance state, the PMC is configured to pin a memory performance state to less than a maximum possible memory performance state available to the computer system”
However, in the analogous art of managing a memory controller with low-power states Ahmad does teach “Wherein, to determine the target performance state, the PMC is configured to pin a memory performance state to less than a maximum possible memory performance state available to the computer system” ([0030] The micro-controller 104 (i.e. PMC) may negotiate with the system to determine a maximum latency that can be tolerated by all devices. The micro-controller may also select a target low-power MC-state and any corresponding parameters accordingly, as well as state sequence data fields if necessary for this target state. The micro-controller 104 may also ensure that any static state data (e.g., SRAM re-repair or static control registers) are pre-saved in the on-die storage 108).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, and Ahmad before him, the effective filing date of the claimed invention, to incorporate Ahmad’s selection of less than maximum performance state into the system disclosed by Severino and Arbel to utilize power management methods in order to increase battery-life ([0002] Ahmad).
Regarding Claim 9, the combination of Severino, Arbel, and Ahmad teaches “The apparatus of claim 8”. Ahmad further discloses:
“Wherein the PMC is configured to pin the memory performance state based on a latency tolerance value received from a particular real-time agent circuit” [0021] A memory controller (i.e. PMC) may also be set into a power-saving state during periods of inactivity. The DRAM is unavailable in non-MC0 states (e.g., an active state), so that the time a memory subsystem can remain in a non-MC0 state is limited. The time it takes to return to the MC0 state may be bounded and within a worst-case latency tolerance of the system (i.e. pin the memory performance state based on a latency tolerance value)).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Severino, Arbel, Ahmad, and further in view of Allen-Ware.
Regarding Claim 10, the combination of Severino, Arbel, and Ahmad teach “The apparatus of claim 9”.
Severino, Arbel, and Ahmad do not teach:
“Wherein the particular real-time agent circuit is a peripheral coupled to a bus of the computer system”
However, in the analogous art of computing system voltage control methods Allen-Ware does teach “Wherein the particular real-time agent circuit is a peripheral coupled to a bus of the computer system” ([0092] For example, the functionality may be implemented with an application specific integrated circuit, in logic implemented in the processing unit 701, in a co-processor on a peripheral device or card, etc. Further, realizations may include fewer or additional components not illustrated in FIG. 7 (e.g., video cards, audio cards, additional network interfaces, peripheral devices (i.e. real-time agent), etc.). The processor unit 701, the storage device(s) 711, and the network interface 713 are coupled to the bus 711).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, Ahmad, and Allen-Ware before him, the effective filing date of the claimed invention, to incorporate Allen-Ware’s various peripheral units coupled to a bus into the system disclosed by Severino, Arbel, and Ahmad to reduce power consumption associated with data centers ([0003] Allen-Ware).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Severino in view of Arbel.
Regarding Claim 11, Severino teaches:
“A method, comprising: receiving, at an interface of a power management circuit (PMC) of a computer system from a plurality of requestors, a plurality of performance state requests” ([C10:L50-57] During normal operation, the Power Processing Unit (PPU) 100 (i.e. requestor)(the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM) can signal to the Power Conversion and Storage Module (PCSM) 110 (i.e. PMC) when it decides that it wishes to change the power state (i.e. performance state requests) of the power domain being controlled by it. In particular, it can assert a request signal over path 120));
“Determining, at the PMC based on the plurality of performance state requests, a target performance state for the computer system having component performance states specified externally to the PMC as being available to the plurality of requestors” ([C10:L56-62] The PCSM 110 (i.e. the PMC) can then be responsive to the asserted request signal on path 120 (i.e. available to the requestor), to undertake the necessary power switching control required to implement the target power state indicated by the pstate signal on path 125, and once those steps have been taken, can assert a paccept signal over path 130 (i.e. external to the PMC) back to the PPU 100 (i.e. the requestor) (the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM));
“Determining, by the PMC based on the target performance state, to permit a transition to an internal performance state that is managed within the PMC” ([C11:L59-62] FIG. 5 is a similar flow diagram to FIG. 4, but illustrates the sequence of steps when the PPU decides that the power state of the domain (i.e. defined internally within the PMC) should be transitioned to a less power saving state (i.e. permit a transition to an internal performance state));
“The internal performance state including at least one component performance state not specified as being available to the plurality of requestors” ([C8:L28-35] It can hence be seen that the PPU (i.e. requestor) components 17, 24 are used to control the functional behavior of components within the controlled power domain to ensure that appropriate actions are taken by those components taking into account the transition in the power state that is being implemented (i.e. the internal performance state has at least one external performance state not specified externally to the PMC; as functional behavior of components are controlled but the behavior of the components are not part of the externally available requests). In contrast, the PCSM (i.e. external to the PMC) components 22, 26 are used to handle the actual switching of the power supply required when transitioning between different power states);
Severino does not teach:
“The computer system having a first power domain and a second power domain”
However, in the analogous art of a system-on-chip (SoC) that includes a memory subsystem, Arbel does teach “The computer system having a first power domain and a second power domain” ([0005] The integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino and Arbel before him, the effective filing date of the claimed invention , to incorporate Arbel’s plurality of master circuits operating in a plurality of power domains in Severino’s integrated circuit for managing power domains to offer an alternative to multi-chip designs with integration of components into a single device to increase overall speed while decreasing size (Arbel [0003]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Severino, Arbel, and further in view of Garg.
Regarding Claim 12, Severino in view of Arbel teaches “The method of claim 11”.
Arbel further discloses:
“Wherein the computer system includes a plurality of agent circuits in the first power domain and one or more memory interface circuits in the second power domain” [0024] Various modules of the IC 100 are in different power domains. For example, the Processing System (PS) 102 ([0019] The PS 102 can be or include one or more processor cores. For example, the PS 102 can include a number of ARM-based embedded processor cores (i.e. a plurality of agent circuits)) is in a first power domain 202; [0024] The Memory Controller (MC) 1 110 and Memory Controller (MC) 2 112 are in one or more third power domain 206);
Severino in view of Garg does not teach:
“Wherein a component performance state of the internal performance state and a component performance state of the target performance differ in a value of a frequency of a crossover clock signal used to transfer data across a boundary between the first power domain and the second power domain”
However, in the analogous art of hierarchical power management (HPM) architecture Garg does disclose “Wherein a component performance state of the internal performance state and a component performance state of the target performance differ in a value of a frequency of a crossover clock signal used to transfer data across a boundary between the first power domain and the second power domain” ([0329] Where the P-unit is determined at 3312 to be the supervisor P-unit (i.e. a component performance state of the internal performance state), the P-unit (at 3314) (i.e. a component performance state of the target performance) sends Memory Class of Service (MCLOS) parameters from the P-unit to another P-unit of a different power domain (e.g., a different IC die) (i.e. data across the fabric boundary); [0266] In some embodiments, the offset value is provided to allow compensation for clock skew, which is a phenomenon whereby a clock signal from a given source may arrive at different circuit components at different times (i.e. different clock frequency values)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, and Garg before him, the effective filing date of the claimed invention, to incorporate Garg’s P-unit sending Memory Class of Service (MCLOS) to other P-units into the system disclosed by Severino and Arbel to maximize power and performance (PnP) for the system-on-chip (SoC) ([0002] Garg).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Severino, Arbel, Garg, and further in view of Maatta et al. (US 2005/0270736 A1).
Regarding Claim 13, The combination of Severino, Arbel, and Garg teaches “The method of Claim 12”.
Garg further discloses:
“Wherein versions of the computer system are usable in a plurality of computing platforms” ([0540] FIG. 55 illustrates a smart device or a computer system or a SoC (System-on-Chip) with HPM, in accordance with some embodiments. In some embodiments, device 5500 represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like).
The combination of Severino, Arbel, and Garg does not teach:
“Wherein the internal performance state is for use of the computer system in a mobile device computing platform”
“But not in one or more other ones of the plurality of computing platforms”
However, in the analogous art of multiple operating modes to accommodate mobile-device and desktop usage Maatta does teach:
“Wherein the internal performance state is for use of the computer system in a mobile device computing platform” ([0039] In its mobile-station operating mode (i.e. internal performance state), equipment 10 looks like any mobile telephone; In the mobile-station operating mode, the multimedia display 13 of the equipment 10 is congruent with the body structure 11 of the equipment 10. Display 13 hereby covers at least a part of a possibly enlarged input part 21. In the case according to the embodiment, the enlarged input part 21 is entirely covered by the display 13. The display part 13 is hereby embedded in its place 19 arranged in body structure 11, whereby together with the mono block body 11 of the equipment 10 it forms a fairly smooth, congruent and straightlined structure without any disadvantageous protruding elements or such, which would essentially increase the thickness of the equipment 10.
“But not in one or more other ones of the plurality of computing platforms” ([0072] In FIG. 6a the equipment 10 is presented its mobile-station mode in which it may be used as a handset manner (i.e. not in one or more other plurality of computer platforms) and in FIG. 6c in its desktop mode in which that may be away from the user's hand. In FIG. 6b is presented intermediate phase when changing between the operating modes is ongoing
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, Garg, and Maatta before him, the effective filing date of the claimed invention, to incorporate Maatta’s mobile-station mode into the system disclosed by Severino, Arbel, and Garg to create ease of use with handheld devices in a table viewing manner ([0010] Maatta).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Severino, Arbel, and further in view of Das (US 2021/0096896 A1).
Regarding Claim 14, Severino, in view of Arbel teaches “The method of claim 11”.
Severino in view of Arbel does not teach:
“Wherein the PMC includes a plurality of transition tables circuits in which a first transition table circuit but not a second transition table circuit includes an entry for the internal performance state”
“Wherein, in response to an occurrence of a first particular state transition, the PMC is configured to cause the first transition table circuit to be used for transition checking until occurrence of a second particular state transition”
“The PMC is configured to cause the second transition table circuit to be used for transition checking until a subsequent occurrence of the first particular state transition”
However, in the analogous art of processor core power management in a virtualized environment Das does disclose:
“Wherein the PMC includes a plurality of transition tables circuits in which a first transition table circuit but not a second transition table circuit includes an entry for the internal performance state” ([0058] The hypervisor 24 (i.e. PMC) determines that the request is directed to a port associated with the VM 38-1, and accesses the conditions table 72. The hypervisor 24 determines that the port matches the condition in the entry 74-1, and sets the P-state of the processor core 18 associated with the VCPU 44-1 to P0. The process 48 receives the request, and executes on the processor core 18 at a P-state of P0; [0029] The hypervisor 24 generates, or has access to, a P-state table 26 (i.e. a first transition table circuit) that correlates the P-states 20 to P-state levels that are exposed to VMs (i.e. an entry for the internal performance state, not involving the second transition table circuit, as the P-state table and C-state table contain different performance states) that are managed by the hypervisor 24; [0030] The hypervisor 24 may also generate, or have access to, a C-state table 30 (i.e. a second transition table circuit) that correlates the C-states 22 to C-state levels that are exposed to VMs that are managed by the hypervisor 24);
“Wherein, in response to an occurrence of a first particular state transition, the PMC is configured to cause the first transition table circuit to be used for transition checking until occurrence of a second particular state transition” (0056] The guest OS 40-1 determines that entry 70-1 identifies the process 48 and indicates that the process 48 should be initiated at the P-state level 28-0. In response to this determination, the guest OS 40-1 sends the request to the hypervisor 24 (i.e. the PMC) to set the P-state of the VCPU (i.e. first transition table circuit to be used for transition checking until occurrence of a second particular state transition) 44-1 to the requested P-state level 28-0 (PSL0). The hypervisor 24 then processes the request as described above; [0059] After the process 48 has serviced the request (i.e. in response to an occurrence of a first particular state transition), the guest OS 40-1 may then send the hypervisor 24 a request to set the VCPU 44-1 to an idle C-state level 32-3 (C3) (i.e. occurrence of a second particular state transition). The hypervisor 24 receives the request and then sets the processor core 18 associated with the VCPU 44-1 to a C-state level of C3);
“The PMC is configured to cause the second transition table circuit to be used for transition checking until a subsequent occurrence of the first particular state transition” ([0059] The hypervisor 24 (i.e. PMC) receives the request and then sets the processor core 18 associated with the VCPU 44-1 to a C-state level of C3. Upon receipt of a subsequent request directed to the respective port, the process described above is repeated, allowing the process 48 to service requests on a processor core 18 at a P-state level of P0, yet when not servicing requests, allow the processor core 18 to be set to an idle C-state level of C3).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, and Das before him, the effective filing date of the claimed invention, to incorporate Das’ hypervisor executing on a processor device of a computing host into the system disclosed by Severino and Arbel to accommodate multiple processor frequencies associated with different processor voltages ([0001] Das).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Severino, Arbel, and further in view of Ahmad.
Regarding Claim 15, Severino in view of Arbel teaches “The method of claim 11”.
Severino in view of Arbel does not teach:
“Wherein determining the target performance state includes pinning, based on a real-time agent maximum performance state setting a memory performance state to less than a maximum possible memory performance state available to the computer system”
However, in the analogous art of managing a memory controller with low-power states Ahmad does teach “Wherein determining the target performance state includes pinning, based on a real-time agent maximum performance state setting a memory performance state to less than a maximum possible memory performance state available to the computer system” ([0030] The micro-controller 104 may negotiate with the system to determine a maximum latency that can be tolerated by all devices. The micro-controller may also select a target low-power MC-state (i.e. target performance state) and any corresponding parameters accordingly, as well as state sequence data fields if necessary for this target state. The micro-controller 104 may also ensure that any static state data (e.g., SRAM re-repair or static control registers) are pre-saved in the on-die storage 108).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, and Ahmad before him, the effective filing date of the claimed invention, to incorporate Ahmad’s dynamic power-gating and frequency changing of a memory controller into the system disclosed by Severino and Arbel to utilize power management methods in order to increase battery-life ([0002] Ahmad).
Claims 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Severino, in view of Arbel.
Regarding Claim 16, Severino teaches:
“An apparatus, comprising: a computer system that includes: a first plurality of circuits within a first power domain” ([C2:L27-29] there is provided an integrated circuit comprising: first circuitry provided within a first power domain);
“A power management circuit (PMC) configured to: receive a set of one or more performance state requests from one or more requestors within the computer system” ([C10:L50-57] During normal operation, the Power Processing Unit (PPU) 100 (i.e. requestor)(the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM) can signal to the Power Conversion and Storage Module (PCSM) 110 (i.e. PMC) when it decides that it wishes to change the power state (i.e. performance state requests) of the power domain being controlled by it. In particular, it can assert a request signal over path 120));
“Permit, based on the set of one or more performance state requests, a transition to an internal performance state defined within the PMC” ([C11:L59-62] FIG. 5 is a similar flow diagram to FIG. 4, but illustrates the sequence of steps when the PPU decides that the power state of the domain (i.e. defined internally within the PMC) should be transitioned to a less power saving state (i.e. permit a transition to an internal performance state));
“The internal performance state having at least one component performance state that is not one of a plurality of performance states specified externally to the PMC as being available to the one or more requestors” ([C8:L28-35] It can hence be seen that the PPU (i.e. requestor) components 17, 24 are used to control the functional behavior of components within the controlled power domain to ensure that appropriate actions are taken by those components taking into account the transition in the power state that is being implemented (i.e. the internal performance state has at least one external performance state not specified externally to the PMC; as functional behavior of components are controlled but the behavior of the components are not part of the externally available requests). In contrast, the PCSM (i.e. external to the PMC) components 22, 26 are used to handle the actual switching of the power supply required when transitioning between different power states);
“Implement transitioning to the internal performance state by causing a change to operation of a particular circuit of the computer system relative to operation of the particular circuit in a particular one of the plurality of performance states” ([C11:L59-62] FIG. 5 is a similar flow diagram to FIG. 4, but illustrates the sequence of steps when the PPU decides that the power state of the domain (i.e. defined internally within the PMC) should be transitioned to a less power saving state (i.e. permit a transition to an internal performance state));
Severino does not teach:
“A second plurality of circuits within a second power domain”
However, in the analogous art of a system-on-chip (SoC) that includes a memory subsystem, Arbel does teach “A second plurality of circuits within a second power domain” ([0016] the memory subsystem includes one or more memory controllers (i.e. a second plurality of circuits) that are in a power domain separate and independent from power domains of master modules (i.e. within a second power domain)).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino and Arbel before him, the effective filing date of the claimed invention , to incorporate Arbel’s multiple memory controllers in separate power domains in Severino’s integrated circuit for managing power domains to offer an alternative to multi-chip designs with integration of components into a single device to increase overall speed while decreasing size (Arbel [0003]).
Regarding Claim 18, Severino in view of Arbel teaches “The apparatus of claim 16”.
Severino further discloses:
“Wherein the plurality of performance states includes component performance states for the first power domain and the second power domain” ([C2:L27-33] In a further example, there is provided an integrated circuit comprising: first circuit means provided within a first power domain; distributed power controller means for controlling transition of the first power domain between a plurality of power states, the distributed power controller means comprising at least power control means in a second power domain);
“A third component performance state for an operating value of the particular circuit” ([C7:L17-18] the further power control circuitry at least partly resides within the third power domain; [C6:L35-38] In one particular example arrangement, the third power domain is constrained to remain in the powered state whilst power is supplied to at least one component within the first power domain and the second power domain).
Severino does not teach:
“A second component performance state for the second power domain”
However, Arbel does disclose “A second component performance state for the second power domain” ([0025] The power supply 200 provides a first voltage VO for the first power domain 202, a second voltage V1 (i.e. a second component performance state) for the second power domain 204).
Regarding Claim 19, Severino in view of Arbel teaches “The apparatus of claim 16”.
Severino further discloses:
“Wherein the PMC is configured to: determine, based on the set of one or more performance state requests received from one or more requestors” ([C10:L50-57] During normal operation, the Power Processing Unit (PPU) 100 (i.e. requestor)(the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM) can signal to the Power Conversion and Storage Module (PCSM) 110 (i.e. PMC) when it decides that it wishes to change the power state (i.e. performance state requests) of the power domain being controlled by it. In particular, it can assert a request signal over path 120));
“A target performance state for the computer system having component performance states within the plurality of performance states specified externally to the PMC as being available to the one or more requestors ([C10:L56-62] The PCSM 110 (i.e. the PMC) can then be responsive to the asserted request signal on path 120 (i.e. available to the requestor), to undertake the necessary power switching control required to implement the target power state indicated by the pstate signal on path 125, and once those steps have been taken, can assert a paccept signal over path 130 (i.e. external to the PMC) back to the PPU 100 (i.e. the requestor) (the PPU 100 consists of associated reset signals received over paths 105, 115, respectively used to communicate with the PCSM));
“Determine, based on the target performance state, to transition to the internal performance state” ([C11:L59-62] FIG. 5 is a similar flow diagram to FIG. 4, but illustrates the sequence of steps when the PPU decides that the power state of the domain (i.e. defined internally within the PMC) should be transitioned to a less power saving state (i.e. permit a transition to an internal performance state)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Severino, Arbel, and further in view of Nakamura.
Regarding Claim 20, Severino in view of Arbel teaches “The apparatus of claim 19”.
Severino in view of Arbel does not teach:
“Wherein, to permit the transition, the PMC is configured to select one of a plurality of transition table circuits based on a current transition selection mode”
“Determine whether the transition is permitted by presenting the target performance state to the selected transition table circuit”
However, in the analogous art of information processing within a selected power control mode Nakamura does teach:
“Wherein, to permit the transition, the PMC is configured to select one of a plurality of transition table circuits based on a current transition selection mode” ([0083] The performance control unit 217 refers to the mode transition table to identify, for each processor, the mode transition condition satisfied by the state of the processor, and changes the power control mode to the one pertaining to the identified mode transition condition);
“Determine whether the transition is permitted by presenting the target performance state to the selected transition table circuit” ([0083] The performance control unit 217 refers to the mode transition table to identify, for each processor, the mode transition condition satisfied by the state of the processor, and changes the power control mode to the one pertaining to the identified mode transition condition).
Accordingly, it would have been obvious to a person having ordinary skill in the art, having the teachings of Severino, Arbel, and Nakamura before him, the effective filing date of the claimed invention , to incorporate Nakamura’s transition and power control tables into the system disclosed by Severino and Arbel to provide more advanced image processing functionality ([0003] Nakamura).
Conclusion
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/J.L.R./
Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
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