CTNF 18/954,017 CTNF 80000 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy of Japanese patent application number 2018-143491, filed on July 31, 2018, has been received and made of record in parent US Application No. 17/261,059. Information Disclosure Statement The information disclosure statements (lDS) submitted on November 21, 2024 and June 3, 2025 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 08-34 AIA Claim s 1-9, 11-13, 15, 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5-6 of U.S. Patent No. 11,482,550 in view of Nakagawa (WO 2018/198486; the Examiner also notes that for purposes of examination, the Examiner will refer to the machine translation), and Yi et al. (US Pub. 2014/0252420) . Although the claims at issue are not identical, they are not patentably distinct from each other because : Regarding claims 1, 17, and 20 : Application Patent 11,482,550 Claim 1 Claim 5 1. A light detecting device, comprising: a semiconductor layer comprising a front surface and a back surface, wherein the back surface is opposite the front surface; 5. An imaging device, comprising: a semiconductor layer having a front surface and a back surface, the back surface being on an opposite side of the semiconductor layer from the front surface; a photoelectric converter, wherein the photoelectric converter is embedded in the semiconductor layer, and wherein the photoelectric converter generates electric charges corresponding to an amount of received light; and a photoelectric converter that is embedded in the semiconductor layer and that generates electric charges corresponding to a received light amount; and a transfer section that transfers the electric charges from the photoelectric converter to a single transfer destination, wherein the transfer section comprises a first portion and a second portion in a cross-sectional view, the first portion and the second portion each extending from the front surface to the back surface of the semiconductor layer, a transfer section that includes a first trench gate and a second trench gate and that transfers the electric charges from the photoelectric converter to a single transfer destination via the first trench gate and the second trench gate, the first trench gate and the second trench gate each extending from the front surface toward the back surface of the semiconductor layer and into the photoelectric converter, wherein the first portion has a first length from the front surface, wherein the first trench gate has a first length from the front surface to the photoelectric converter, wherein the second portion has a second length from the front surface, the second length being shorter than the first length, and wherein the second trench gate has a second length from the front surface to the photoelectric converter, the second length being shorter than the first length, and wherein the transfer destination is located between the first portion and the second portion in the cross-sectional view. wherein the transfer destination is located between the first trench gate and the second trench gate. Claim 17 Claim 5 17. The light detecting device according to claim 1, wherein the transfer destination is located between the first portion and the second portion in a plan view. 5. … wherein the transfer destination is located between the first trench gate and the second trench gate. Claim 20 Claims 5 & 6 20. An electronic apparatus comprising a light detecting device, 6. An electronic apparatus comprising the imaging device of claim 5. the light detecting device including: a semiconductor layer comprising a front surface and a back surface, wherein the back surface is opposite the front surface; 5. An imaging device, comprising: a semiconductor layer having a front surface and a back surface, the back surface being on an opposite side of the semiconductor layer from the front surface; a photoelectric converter, wherein the photoelectric converter is embedded in the semiconductor layer, and wherein the photoelectric converter generates electric charges corresponding to an amount of received light; and a photoelectric converter that is embedded in the semiconductor layer and that generates electric charges corresponding to a received light amount; and a transfer section that transfers the electric charges from the photoelectric converter to a single transfer destination, wherein the transfer section comprises a first portion and a second portion in a cross-sectional view, the first portion and the second portion each extending from the front surface to the back surface of the semiconductor layer, a transfer section that includes a first trench gate and a second trench gate and that transfers the electric charges from the photoelectric converter to a single transfer destination via the first trench gate and the second trench gate, the first trench gate and the second trench gate each extending from the front surface toward the back surface of the semiconductor layer and into the photoelectric converter, wherein the first portion has a first length from the front surface, wherein the first trench gate has a first length from the front surface to the photoelectric converter, wherein the second portion has a second length from the front surface, the second length being shorter than the first length, and wherein the second trench gate has a second length from the front surface to the photoelectric converter, the second length being shorter than the first length, and wherein the transfer destination is located between the first portion and the second portion in the cross-sectional view. wherein the transfer destination is located between the first trench gate and the second trench gate. In view of the foregoing, claims 1, 17, and 20 of the pending application are an obvious variant and encompassed by claims 5-6 of US Patent 11,482,550. Regarding claims 2-3 and 6-7 : With respect to claims 2-3 and 6-7 , these claims further include limitation that “the transfer section includes a first transfer transistor and a second transfer transistor”, “the first portion is a trench gate of the first transfer transistor, and wherein the second portion is a trench gate of the second transfer transistor”, “the first portion has a maximum width at the front surface of the semiconductor layer, and wherein the second portion has a maximum width at the front surface of the semiconductor layer”, and “a width of the first portion decreases with increasing distance from the front surface of the semiconductor layer, and wherein a width of the second portions decreases with increasing distance from the front surface of the semiconductor layer”, respectively. In analogous art, Nakagawa (WO 2018198486 A1) discloses that a width (i.e., diameter) of the first transistor trench gate and a width (i.e., diameter) of the second transistor trench gate each have a portion that is widest at the front surface, and decreases toward the back surface from the front surface (paragraphs 0007, 0033, 0037, 0043, and figure 13: 125, 126; the gates 125 and 126 are tapered). Nakagawa teaches that the use of a width of the first transistor trench gate and a width of the second transistor trench gate, that each have a portion that is widest at the front surface, and decreases toward the back surface from the front surface is preferred in order to increase the transfer efficiency (paragraphs 0037, 0043). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a width of the first transistor trench gate and a width of the second transistor trench gate, that each have a portion that is widest at the front surface, and decreases toward the back surface from the front surface is preferred in order to increase the transfer efficiency, in order to increase the transfer efficiency, as suggested by Nakagawa. Regarding claims 4-5 : With respect to claims 4-5 , these claims further include limitation that “the first trench gate is connected to a first drive signal line, and wherein the second trench gate is connected to a second drive signal line”, and “the first transfer transistor and the second transfer transistor are configured to be driven independently of one another”, respectively. In analogous art, Nakagawa (WO 2018198486 A1) discloses that the first trench gate is connected to a first drive signal line, and wherein the second trench gate is connected to a second drive signal line, and that the first transfer transistor and the second transfer transistor are configured to be driven independently of one another (paragraph 0052, and figure 15). Nakagawa teaches that having the first trench gate connected to a first drive signal line, and the second trench gate connected to a second drive signal line, and the first transfer transistor and the second transfer transistor being configured to be driven independently of one another is preferred in order to make it possible to change or adjust the transfer path according to the timing and voltage (paragraph 0052, and figure 15). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the first trench gate connected to a first drive signal line, and wherein the second trench gate is connected to a second drive signal line, and the first transfer transistor and the second transfer transistor are configured to be driven independently of one another, in order to make it possible to change or adjust the transfer path according to the timing and voltage, as suggested by Nakagawa. Regarding claims 8, 9, and 11 : With respect to claims 8, 9, and 11 , these claims further include limitations that “the single transfer destination is an electric charge-voltage converter”, “the single transfer destination is an electric-charge-voltage holding section”, and “the single transfer destination is a floating diffusion”, respectively. In analogous art, Nakagawa (WO 2018198486 A1) discloses the use of an imaging device in which the transfer destination is an electric charge-voltage converter and/or floating diffusion (paragraphs 0028-0030, and figure 2-3: 100 & 300; the charge is transferred to the floating diffusion 300, which performs electric charge-voltage conversion/holding). The use of a an electric charge-voltage converter and/or floating diffusion as a transfer destination is well known in the art in order to allow the pixel signals to be read out of the image senor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a transfer destination that is an electric charge-voltage converter and/or floating diffusion, in order to readout the pixel signals, as is common in the art. Regarding claim 12 : With respect to claim 12 , this claim further include limitations that “the photoelectric converter is a photodiode”. In analogous art, Nakagawa (WO 2018198486 A1) discloses the use of an imaging device in which the photoelectric converter is a photodiode (paragraph 0026, and figure 2-3: 200). The use of a photodiode is well known in the art in order to convert incident light into an electric signal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the use of a photodiode, in the art in order to convert incident light into an electric signal, as is common in the art. Regarding claim 13 : With respect to claim 13 , this claim further include limitations that “the back surface of the semiconductor layer is a light incident surface”. Official Notice is taken that the concepts and advantages of imaging device in which the back surface of the semiconductor layer is a light incident surface are notoriously well known and expected in the art in order to improve image sensing efficiency since the incident light is not blocked by the wiring formed on the front surface. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form the back surface of the semiconductor layer as the light incident surface, in order to improve image sensing efficiency since the incident light is not blocked by the wiring formed on the front surface, as is well known in the art. Regarding claim 15 : With respect to claim 15 , this claim further include limitations that “the transfer section at least partially overlaps the photoelectric converter in a plan view”. In analogous art, Yi et al. (US Pub. 2014/0252420) discloses the use of an imaging device in which the transfer section at least partially overlaps the photoelectric converter in a plan view (paragraph 0042, and figure 2A-2C: 22, PD; each of the trench gates 22, that extend into the substrate, overlap with the photodiode PD in the plan view). The overlapping of gates and photodiodes is commonly used in the art in order to efficiently transfer the charge out of the photodiode. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the overlap of the transfer section with the photoelectric converter in a plan view, in order to efficiently transfer the charge out of the photodiode, as is common in the art. Regarding claim 18 : With respect to claim 18 , this claim further include limitations “an insulating layer is disposed between the first portion and the semiconductor layer, between the first portion and the photoelectric converter, between the second portion and the semiconductor layer, and between the second portion and the photoelectric converter”. In analogous art, Nakagawa (WO 2018198486 A1) discloses the use of an imaging device in which an insulating layer is disposed between the first portion and the semiconductor layer, between the first portion and the photoelectric converter, between the second portion and the semiconductor layer, and between the second portion and the photoelectric converter (paragraph 0028, and figure 2: 102). The use of insulating layers are well known in the art in order to prevent charge leakage/transfer between components. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include an insulating layer is disposed between the first portion and the semiconductor layer, between the first portion and the photoelectric converter, between the second portion and the semiconductor layer, and between the second portion and the photoelectric converter, in order to prevent charge leakage/transfer between components, as is common in the art. Regarding claim 19 : With respect to claim 19 , this claim further include limitations that “a light shielding section surrounds the photoelectric converter”. Official Notice is taken that the concepts and advantages of imaging device which includes a light shielding section surrounds the photoelectric converter are notoriously well known and expected in the art in order to control the incident light level to the photosensitive area, as well as to prevent incident light from reaching peripheral circuitry which may cause noise. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a light shielding section surrounds the photoelectric converter, in order to control the incident light level to the photosensitive area, as well as to prevent incident light from reaching peripheral circuitry which may cause noise, as is well known in the art . 08-34 AIA Claim s 1-9, 11-13, 15, and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5-6 of U.S. Patent No. 12,230,654 in view of Nakagawa (WO 2018/198486; the Examiner also notes that for purposes of examination, the Examiner will refer to the machine translation), and Yi et al. (US Pub. 2014/0252420) . Although the claims at issue are not identical, they are not patentably distinct from each other because : Regarding claims 1, 17, and 20 : Application Patent 12,230,654 Claim 1 Claims 1 & 5 1. A light detecting device, comprising: a semiconductor layer comprising a front surface and a back surface, wherein the back surface is opposite the front surface; 1. A light detecting device, comprising: a semiconductor layer having a front surface and a back surface, the back surface being on an opposite side of the front surface; a photoelectric converter, wherein the photoelectric converter is embedded in the semiconductor layer, and wherein the photoelectric converter generates electric charges corresponding to an amount of received light; and a photoelectric converter that is embedded in the semiconductor layer and generates electric charges corresponding to a received light amount; and a transfer section that transfers the electric charges from the photoelectric converter to a single transfer destination, wherein the transfer section comprises a first portion and a second portion in a cross-sectional view, the first portion and the second portion each extending from the front surface to the back surface of the semiconductor layer, a transfer section that includes a first portion and a second portion and transfers the electric charges from the photoelectric converter to a single transfer destination, the first portion and the second portion each extending from the front surface to the back surface of the semiconductor layer, wherein the first portion has a first length from the front surface, wherein the first portion has a first length from the front surface to a bottom portion of the first portion which is disposed between the front surface of the semiconductor layer and the back surface of the semiconductor layer, wherein the second portion has a second length from the front surface, the second length being shorter than the first length, and the second portion has a second length from the front surface to a bottom portion of the second portion which is disposed between the front surface of the semiconductor layer and the back surface of the semiconductor layer, the second length being shorter than the first length, … wherein the transfer destination is located between the first portion and the second portion in the cross-sectional view. 5. The light detecting device according to claim 1, wherein the transfer destination is located between the first portion and the second portion. Claim 17 Claim 5 17. The light detecting device according to claim 1, wherein the transfer destination is located between the first portion and the second portion in a plan view. 5. The light detecting device according to claim 1, wherein the transfer destination is located between the first portion and the second portion. Claim 20 Claims 1 & 5 20. An electronic apparatus comprising a light detecting device, the light detecting device including: a semiconductor layer comprising a front surface and a back surface, wherein the back surface is opposite the front surface; 1. A light detecting device, comprising: a semiconductor layer having a front surface and a back surface, the back surface being on an opposite side of the front surface; a photoelectric converter, wherein the photoelectric converter is embedded in the semiconductor layer, and wherein the photoelectric converter generates electric charges corresponding to an amount of received light; and a photoelectric converter that is embedded in the semiconductor layer and generates electric charges corresponding to a received light amount; and a transfer section that transfers the electric charges from the photoelectric converter to a single transfer destination, wherein the transfer section comprises a first portion and a second portion in a cross-sectional view, the first portion and the second portion each extending from the front surface to the back surface of the semiconductor layer, a transfer section that includes a first portion and a second portion and transfers the electric charges from the photoelectric converter to a single transfer destination, the first portion and the second portion each extending from the front surface to the back surface of the semiconductor layer, wherein the first portion has a first length from the front surface, wherein the first portion has a first length from the front surface to a bottom portion of the first portion which is disposed between the front surface of the semiconductor layer and the back surface of the semiconductor layer, wherein the second portion has a second length from the front surface, the second length being shorter than the first length, and the second portion has a second length from the front surface to a bottom portion of the second portion which is disposed between the front surface of the semiconductor layer and the back surface of the semiconductor layer, the second length being shorter than the first length, … wherein the transfer destination is located between the first portion and the second portion in the cross-sectional view. 5. The light detecting device according to claim 1, wherein the transfer destination is located between the first portion and the second portion. In view of the foregoing, claims 1, 17, and 20 of the pending application are an obvious variant and encompassed by claims 1 and 5 of US Patent 12,230,654. Regarding claims 2-3 and 6-7 : With respect to claims 2-3 and 6-7 , these claims further include limitation that “the transfer section includes a first transfer transistor and a second transfer transistor”, “the first portion is a trench gate of the first transfer transistor, and wherein the second portion is a trench gate of the second transfer transistor”, “the first portion has a maximum width at the front surface of the semiconductor layer, and wherein the second portion has a maximum width at the front surface of the semiconductor layer”, and “a width of the first portion decreases with increasing distance from the front surface of the semiconductor layer, and wherein a width of the second portions decreases with increasing distance from the front surface of the semiconductor layer”, respectively. In analogous art, Nakagawa (WO 2018198486 A1) discloses that a width (i.e., diameter) of the first transistor trench gate and a width (i.e., diameter) of the second transistor trench gate each have a portion that is widest at the front surface, and decreases toward the back surface from the front surface (paragraphs 0007, 0033, 0037, 0043, and figure 13: 125, 126; the gates 125 and 126 are tapered). Nakagawa teaches that the use of a width of the first transistor trench gate and a width of the second transistor trench gate, that each have a portion that is widest at the front surface, and decreases toward the back surface from the front surface is preferred in order to increase the transfer efficiency (paragraphs 0037, 0043). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a width of the first transistor trench gate and a width of the second transistor trench gate, that each have a portion that is widest at the front surface, and decreases toward the back surface from the front surface is preferred in order to increase the transfer efficiency, in order to increase the transfer efficiency, as suggested by Nakagawa. Regarding claims 4-5 : With respect to claims 4-5 , these claims further include limitation that “the first trench gate is connected to a first drive signal line, and wherein the second trench gate is connected to a second drive signal line”, and “the first transfer transistor and the second transfer transistor are configured to be driven independently of one another”, respectively. In analogous art, Nakagawa (WO 2018198486 A1) discloses that the first trench gate is connected to a first drive signal line, and wherein the second trench gate is connected to a second drive signal line, and that the first transfer transistor and the second transfer transistor are configured to be driven independently of one another (paragraph 0052, and figure 15). Nakagawa teaches that having the first trench gate connected to a first drive signal line, and the second trench gate connected to a second drive signal line, and the first transfer transistor and the second transfer transistor being configured to be driven independently of one another is preferred in order to make it possible to change or adjust the transfer path according to the timing and voltage (paragraph 0052, and figure 15). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the first trench gate connected to a first drive signal line, and wherein the second trench gate is connected to a second drive signal line, and the first transfer transistor and the second transfer transistor are configured to be driven independently of one another, in order to make it possible to change or adjust the transfer path according to the timing and voltage, as suggested by Nakagawa. Regarding claims 8, 9, and 11 : With respect to claims 8, 9, and 11 , these claims further include limitations that “the single transfer destination is an electric charge-voltage converter”, “the single transfer destination is an electric-charge-voltage holding section”, and “the single transfer destination is a floating diffusion”, respectively. In analogous art, Nakagawa (WO 2018198486 A1) discloses the use of an imaging device in which the transfer destination is an electric charge-voltage converter and/or floating diffusion (paragraphs 0028-0030, and figure 2-3: 100 & 300; the charge is transferred to the floating diffusion 300, which performs electric charge-voltage conversion/holding). The use of a an electric charge-voltage converter and/or floating diffusion as a transfer destination is well known in the art in order to allow the pixel signals to be read out of the image senor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a transfer destination that is an electric charge-voltage converter and/or floating diffusion, in order to readout the pixel signals, as is common in the art. Regarding claim 12 : With respect to claim 12 , this claim further include limitations that “the photoelectric converter is a photodiode”. In analogous art, Nakagawa (WO 2018198486 A1) discloses the use of an imaging device in which the photoelectric converter is a photodiode (paragraph 0026, and figure 2-3: 200). The use of a photodiode is well known in the art in order to convert incident light into an electric signal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the use of a photodiode, in the art in order to convert incident light into an electric signal, as is common in the art. Regarding claim 13 : With respect to claim 13 , this claim further include limitations that “the back surface of the semiconductor layer is a light incident surface”. Official Notice is taken that the concepts and advantages of imaging device in which the back surface of the semiconductor layer is a light incident surface are notoriously well known and expected in the art in order to improve image sensing efficiency since the incident light is not blocked by the wiring formed on the front surface. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form the back surface of the semiconductor layer as the light incident surface, in order to improve image sensing efficiency since the incident light is not blocked by the wiring formed on the front surface, as is well known in the art. Regarding claim 15 : With respect to claim 15 , this claim further include limitations that “the transfer section at least partially overlaps the photoelectric converter in a plan view”. In analogous art, Yi et al. (US Pub. 2014/0252420) discloses the use of an imaging device in which the transfer section at least partially overlaps the photoelectric converter in a plan view (paragraph 0042, and figure 2A-2C: 22, PD; each of the trench gates 22, that extend into the substrate, overlap with the photodiode PD in the plan view). The overlapping of gates and photodiodes is commonly used in the art in order to efficiently transfer the charge out of the photodiode. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the overlap of the transfer section with the photoelectric converter in a plan view, in order to efficiently transfer the charge out of the photodiode, as is common in the art. Regarding claim 18 : With respect to claim 18 , this claim further include limitations “an insulating layer is disposed between the first portion and the semiconductor layer, between the first portion and the photoelectric converter, between the second portion and the semiconductor layer, and between the second portion and the photoelectric converter”. In analogous art, Nakagawa (WO 2018198486 A1) discloses the use of an imaging device in which an insulating layer is disposed between the first portion and the semiconductor layer, between the first portion and the photoelectric converter, between the second portion and the semiconductor layer, and between the second portion and the photoelectric converter (paragraph 0028, and figure 2: 102). The use of insulating layers are well known in the art in order to prevent charge leakage/transfer between components. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include an insulating layer is disposed between the first portion and the semiconductor layer, between the first portion and the photoelectric converter, between the second portion and the semiconductor layer, and between the second portion and the photoelectric converter, in order to prevent charge leakage/transfer between components, as is common in the art. Regarding claim 19 : With respect to claim 19 , this claim further include limitations that “a light shielding section surrounds the photoelectric converter”. Official Notice is taken that the concepts and advantages of imaging device which includes a light shielding section surrounds the photoelectric converter are notoriously well known and expected in the art in order to control the incident light level to the photosensitive area, as well as to prevent incident light from reaching peripheral circuitry which may cause noise. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include a light shielding section surrounds the photoelectric converter, in order to control the incident light level to the photosensitive area, as well as to prevent incident light from reaching peripheral circuitry which may cause noise, as is well known in the art . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 10, 14, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2020/0135781: note this is the US Application that corresponding to the international application WO2018198486A1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISS S YODER III whose telephone number is (571)272-7323. The examiner can normally be reached M-F 9:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at (571) 272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISS S YODER III/Examiner, Art Unit 2638 Application/Control Number: 18/954,017 Page 2 Art Unit: 2638 Application/Control Number: 18/954,017 Page 3 Art Unit: 2638 Application/Control Number: 18/954,017 Page 4 Art Unit: 2638 Application/Control Number: 18/954,017 Page 5 Art Unit: 2638 Application/Control Number: 18/954,017 Page 6 Art Unit: 2638 Application/Control Number: 18/954,017 Page 7 Art Unit: 2638 Application/Control Number: 18/954,017 Page 8 Art Unit: 2638 Application/Control Number: 18/954,017 Page 9 Art Unit: 2638 Application/Control Number: 18/954,017 Page 10 Art Unit: 2638 Application/Control Number: 18/954,017 Page 11 Art Unit: 2638 Application/Control Number: 18/954,017 Page 12 Art Unit: 2638 Application/Control Number: 18/954,017 Page 13 Art Unit: 2638 Application/Control Number: 18/954,017 Page 14 Art Unit: 2638 Application/Control Number: 18/954,017 Page 15 Art Unit: 2638 Application/Control Number: 18/954,017 Page 16 Art Unit: 2638 Application/Control Number: 18/954,017 Page 17 Art Unit: 2638 Application/Control Number: 18/954,017 Page 18 Art Unit: 2638 Application/Control Number: 18/954,017 Page 19 Art Unit: 2638 Application/Control Number: 18/954,017 Page 20 Art Unit: 2638 Application/Control Number: 18/954,017 Page 21 Art Unit: 2638 Application/Control Number: 18/954,017 Page 22 Art Unit: 2638 Application/Control Number: 18/954,017 Page 23 Art Unit: 2638 Application/Control Number: 18/954,017 Page 24 Art Unit: 2638 Application/Control Number: 18/954,017 Page 25 Art Unit: 2638 Application/Control Number: 18/954,017 Page 26 Art Unit: 2638 Application/Control Number: 18/954,017 Page 27 Art Unit: 2638
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