DETAILED ACTION
This office action is in response to the application filed on 11/20/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1 and 10 are objected to because of the following informalities: Claim 1 line 23 “a connection destination” this should be “the connection destination”. Claim 10 line 2 “a voltage between” this should be “the voltage between”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu US 2025/0260313 in view of Kodera US 2021/0305908.
Regarding Claim 1, Liu teaches (Figures 7 and 14-16) a power conversion device (1400) comprising: a plurality of terminals to which a single-phase AC power supply (grid) or a multi-phase AC power supply is connected as an external power supply; a power conversion circuit (rectifier) including multiple power semiconductor devices (Q switches), the multiple power semiconductor devices including a first pair of power semiconductor devices (Q1-Q2) and a second pair of power semiconductor devices (Qa1-Qa2), the first pair of power semiconductor devices corresponding to a specific phase of the multiple phases of the multi-phase AC power supply (positive phase), the second pair of power semiconductor devices corresponding to another phase different from the specific phase of the multiple phases (negative phase); a phase switching circuit (Qa3-Qa4) configured to switch a connection destination of the second pair of power semiconductor devices (Q3a and Q3b) between the specific phase and the other phase (positive and negative phases); and a control circuit (710 and 702) configured to control operations of the power conversion circuit and the phase switching circuit, the control being performed by, when the single-phase AC power supply is connected to the terminals (see fig. 14), turning on a predetermined power semiconductor device among the multiple power semiconductor devices (Q1, fig. 15a, T0), detecting a zero-crossing point at which a power supply voltage from the single-phase AC power supply zero-crosses in a state where the predetermined power semiconductor device is turned on (t1-t2, 15a), the zero-crossing point being detected based on a voltage between contact points of the phase switching circuit (Q3a-Q4a), and switching a connection destination (by turning on Q3a-Q4a) of the second pair of power semiconductor devices to the specific phase by operating the phase switching circuit (Q3a-Q4a)within a zero period following the zero-crossing point (at t2). (For Example: Par. 147-170)
Liu does not teach a phase switching circuit including a relay circuit.
Kodera teaches (Figure 2-3) a phase switching circuit (Qa3-Qa4) including a relay circuit. (For example: Par. 24-30)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a phase switching circuit including a relay circuit as taught by Kodera to provide inrush current protection and enable operation from different phases.
Regarding Claim 2, Liu teaches (Figures 7 and 14-16) wherein the control circuit (710 and 702) is configured to turn on the predetermined power semiconductor device located on a high side among the multiple power semiconductor devices (Q1), the turning on being performed when the power supply voltage from the single-phase AC power supply is at a negative peak (see fig. 15a, before t0). (For Example: Par. 147-170)
Regarding Claim 6, Liu teaches (Figures 7 and 14-16) wherein the control circuit is configured to turn on the predetermined power semiconductor device located on a low side (q2) among the multiple power semiconductor devices, the turning on being performed when the power supply voltage from the single-phase AC power supply is at a positive peak (after T9, Fig. 15a). (For Example: Par. 147-170 and 180-182)
Regarding Claim 10, Liu teaches (Figures 7 and 14-16) wherein the zero period (t1-t2) is a period of time during which a voltage between contact points of the relay circuit is within a predetermined threshold range (operation range determined by the system) starting from the zero-crossing point (from 0 to -0.1). (For Example: Par. 147-170)
Regarding Claim 11, Liu teaches (Figures 7 and 14-16) wherein the control circuit (710 and 702) is configured to, after the phase switching circuit (q3-q4) is operated in the zero period (fig. 15a, t2), turn off the predetermined power semiconductor device having been turned on (at t9), and start power conversion to convert AC power from the single-phase AC power supply into DC power after the predetermined power semiconductor device is turned off (normalized operation after t9). (For Example: Par. 147-170 an d180-182)
Liu does not teach wherein the control circuit is configured to, after the relay circuit is operated in the zero period.
Kodera teaches (Figure 2-3 and 5) wherein the control circuit (11) is configured to, after the relay circuit is operated in the zero period (fig. 5, t6). (For example: Par. 24-30)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein the control circuit is configured to, after the relay circuit is operated in the zero period, as taught by Kodera to provide inrush current protection and enable operation from different phases.
Allowable Subject Matter
Claim 3-5 and 7-9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 3; prior art of record fails to disclose either by itself or in combination: “…wherein the zero period is a period of time during which an increase amount of the power supply voltage from the single-phase AC power supply is positive after the predetermined power semiconductor device on the high side is turned on.”
Claim 4; prior art of record fails to disclose either by itself or in combination: “…configured to turn off the predetermined power semiconductor device on the high side having been turned on, the turning off being performed when the power supply voltage from the single-phase AC power supply is at a positive peak immediately after the relay circuit is operated in the zero period. “
Claim 7; prior art of record fails to disclose either by itself or in combination: “…wherein the zero period is a period of time during which an increase amount of the power supply voltage from the single-phase AC power supply is negative after the predetermined power semiconductor device on the low side is turned on.”
Claim 8; prior art of record fails to disclose either by itself or in combination: “…the control circuit is configured to turn off the predetermined power semiconductor device on the low side having been turned on, the turning off being performed when the power supply voltage from the single-phase AC power supply is at a negative peak immediately after the relay circuit is operated in the zero period. “
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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