Prosecution Insights
Last updated: May 29, 2026
Application No. 18/954,234

ADDRESS ASSIGNMENT

Non-Final OA §103
Filed
Nov 20, 2024
Priority
Dec 21, 2023 — DE 102023136176.7
Examiner
SUN, SCOTT C
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
581 granted / 660 resolved
+33.0% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
10 currently pending
Career history
675
Total Applications
across all art units

Statute-Specific Performance

§101
6.1%
-33.9% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
13.7%
-26.3% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 660 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-7, 9-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Blaine (US 20140336821 A1) in view of Dress (pub # US 20190372903 A1). Regarding claim 1, Blaine discloses method for assigning an address to an electronic device (assigning network addresses to all subordinate/slave devices in the network, paragraph 25), the method comprising: a) sending a general command (broadcasting a message in the form of device discovery request on the network, paragraph 25) from a controller (controlling device, paragraph 25) of a circuit arrangement to all electronic devices of the circuit arrangement (by definition of broadcasting, paragraph 25), wherein the general command prompts each electronic device to start sending a respective unique identifier (UID) of the respective electronic device (device identifiers, paragraph 25); d) sending an electrical parameter from the active electronic device to the controller (product type, etc., paragraph 26); sending the respective UIDs from the electronic devices (send device identifiers to the controller in response to the discovery request; paragraph 25); e) determining a property of the active electronic device from the electrical parameter (fields that uniquely identify that particular device; note all of the devices are electrical components, shown in figure 2); and f) assigning an address to the active electronic device from a predetermined set of addresses (assigning network address, paragraph 25, unique factory network address; 26). Blaine does not disclose explicitly arbitration amongst the devices using parallel transmission. However, Dress discloses b) sending the respective UIDs from the electronic devices bit-by-bit in parallel (parallel data, paragraph 33); c) performing a bit-by-bit arbitration (arbitration by arbiter 130, paragraph 33, using a round-robin scan through 3-bit flags, paragraph 36) among the electronic devices based on the UIDs until only one electronic device remains active (when multiple data messages/packets arrive, arbiter determines which message or packet is processed, paragraph 30). Furthermore, teachings of Blaine and Dress are from the same field of networked devices. Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Blaine with Dress to use a parallel data transfers system with an arbiter to control multiple devices communicating in parallel for the benefit of resolving bus conflicts and enforce data priorities when multiple data arrive simultaneously. Regarding claim 2, the above combination discloses the Regarding claim 2, the above combination discloses the method according to claim 1, wherein steps a) to f) are repeated continuously until all electronic devices of the circuit arrangement are assigned an address, wherein, after each repetition cycle, assigned addresses and electronic devices with assigned addresses are left out for the following repetition cycles (repeated until all un-configured devices are assigned a network address; devices already configured will no longer respond to the discovery request, paragraph 25, Blaine) Regarding claim 3, the above combination discloses the method according to claim 1, wherein the electrical parameter is selected from the group consisting of: a voltage; a resistance; a current (examiner notes that given Blaine’s teachings of device type, identifiers, and other manufacturer’s information, it would have been obvious to have voltage, resistance, or current for devices such as pumps, sensors, filters, and heaters shown in figure 2). Regarding claim 4, the above combination discloses the method according to claim 1, wherein the electrical parameter is predetermined by at least one of a component of the electronic device and an external supply source (devices such as pumps, sensors, filters, and heaters shown in figure 2; manufacturer’s information as explained in paragraph 26, Blaine). Regarding claim 5, the above combination discloses the method according to claim 1, wherein the electrical parameter is predetermined by at least one of an application- specific resistance, an application-specific capacitance, and an application-specific inductance of at least one component of the electronic device (examiner notes that given Blaine’s teachings of device type, identifiers, and other manufacturer’s information, it would have been obvious to have resistance, capacitance, or inductance for devices such as pumps, sensors, filters, and heaters shown in figure 2). Regarding claim 6, the above combination discloses the method according to claim 1, wherein step d) comprises sending an application-specific voltage from the active electronic device to the controller, wherein the device-specific voltage is dependent on an application-specific resistance of a component of the electronic device, wherein the component is an application-specific resistor (examiner notes that given Blaine’s teachings of device type, identifiers, and other manufacturer’s information, it would have been obvious to have voltage and resistance for devices such as pumps, sensors, filters, and heaters shown in figure 2). Regarding claim 7, the above combination discloses the method according to claim 1, wherein the property determined in step c) is selected from the group consisting of: a position of the electronic device; a function of the electronic device; a type of the electronic device (device information from the manufacturer; paragraph 26, Blaine). Regarding claim 9, the above combination discloses the method according to claim 1, further comprising step b1) performed after step b), wherein step b1) comprises receiving the UIDs of the electronic devices with the controller (receiving identifiers from the slave devices; paragraph 25, Blaine). Regarding claim 10, the above combination discloses the method according to claim 1, wherein the UIDs are sent via an interconnection of the circuit arrangement, wherein the interconnection at least partially interconnects the electronic devices and the controller (RS bus, paragraph 25, Blaine). Regarding claim 11, the above combination discloses the method according to claim 1, wherein at least one of the set of addresses, the general command and the bit-by-bit arbitration is defined in a communication protocol (RS serial bus protocol, paragraph 25, Blaine). Regarding claim 12, the above combination discloses the method according to claim 1, wherein the electronic device is a part of a network (network shown in figure 1) and wherein the address is a network address (network address, paragraph 25, Blaine). Regarding claims 13, examiner notes this claim is substantially similar to claim 1 above. The same grounds of rejection are applied. Regarding claim 14, the above combination discloses the electronic device according to claim 13, wherein the electronic device comprises at least one logic circuit for communication, specifically for performing the bit-by-bit arbitration (circuit details of the arbiter shown in figures, Dress) Regarding claim 15, the above combination discloses the electronic device according to claim 13, wherein the electronic device comprises at least one buffer for buffering the UIDs bit-by-bit for the bit-by-bit arbitration (FIFOs 110, paragraph 32, Dress). Regarding claim 16, the above combination discloses the electronic device according to claim 13, wherein the electronic device comprises at least one component providing an application-specific electrical parameter (manufacturer’s information on the devices; paragraph 26, Blaine). Regarding claims 17, examiner notes this claim is substantially similar to claim 1 above. The same grounds of rejection are applied. Regarding claim 18, the above combination discloses the circuit arrangement according to claim 17, wherein the circuit arrangement comprises at least one printed circuit board (implied by the various computer elements discussed in paragraph 35; Blaine). Regarding claim 19, the above combination discloses the circuit arrangement according to claim 17, further comprising at least one supply source configured for supplying at least one of an application-specific voltage and an application-specific current to at least one electronic device of the circuit arrangement (examiner notes that given Blaine’s teachings of device type, identifiers, and other manufacturer’s information, it would have been obvious to have voltage or current for devices such as pumps, sensors, filters, and heaters shown in figure 2). Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: prior arts of record disclose network discovery and address assignment, including arbitrating amongst multiple network devices. However, prior arts of record do not teach or suggest, inter alia, that the bit-by-bit arbitration process further includes the steps, performed by each device, calculating a logical disjunction, and either remaining active or go passive depending on the result of logical disjunction. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SCOTT C SUN/Primary Examiner, Art Unit 2181
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Prosecution Timeline

Nov 20, 2024
Application Filed
Mar 27, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+10.7%)
2y 5m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 660 resolved cases by this examiner. Grant probability derived from career allowance rate.

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