DETAILED ACTION
This Office action is in response to the amendment of 1/7/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bazarsky et al. (US 2020/0310669 A1) hereinafter Bazarsky et al. in view of Abe et al. (US 2019/0235755 A1) hereinafter Abe et al.
Regarding claim 1, Bazarsky et al. teaches an apparatus, comprising:
a memory device (storage device 106 includes non-volatile memory 110 Paragraph [0025]); and
a controller coupled with the memory device (storage device 106 includes controller 108 Paragraph [0023]-[0025]) and configured to cause the apparatus to:
receive a first command to write first data to a first block of the memory device, the first block associated with a first logical address and a first physical address (a write request is received from a host device, the request including the data, logical address and physical address Paragraph [0033]);
identify an entry associated with a second logical address and a second physical address in a change log in response to receiving the first command (the OUO cache logs any updates or changes made to entries in the L2P cache, where the OUO cache is configured like the compressed L2P cache of Table 1 having the entry number, logical address, physical address Paragraph [0036]);
modify the entry associated with the change log to include information associated with the first command in response to receiving the first command and identifying the entry (the OUO cache may be updated to log the changes of rewriting FMUs Paragraph [0038]), the entry of the change log comprising a first field indicating a block address of the memory device (in response to relocating the data, the OUO cache is updated to reflect that the logical address associated with the data has been linked to a new physical address Paragraph [0044]), and a third field indicating a … state indicative of whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device (a version indicator of the cache entry in the compressed L2P table is incremented which indicates that the cache entry is currently storing partially outdated information and that a newer version may be available Paragraph [0048]-[0049]).
Bazarsky et al. does not appear to explicitly teach, however, Abe et al. teaches a second field indicating a length of data indicated by the entry (each record in the LP conversion table shows information on chunks and mapping between the chunks and compressed-chunk recording positions. Specifically, the data specified by the LA field of the record and is compressed in the overwrite space and stored an area with length field 44D starting from an address specified by the PA field Paragraph [0117]). Abe et al. further teaches a third field indicating a compression state indicative of whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device (the page management table includes a compression function existence flag 40E indicative of whether the storage device providing the physical page has a compression function Paragraph [0159]).
The disclosures of Bazarsky et al. and Abe et al., hereinafter BA, are analogous art to the claimed invention because they are in the same field of endeavor of write command processing and/or compression. .
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of BA before them, to modify the teachings of Bazarsky et al. to include the teachings of Abe et al. since both BA teach writing data to a logical address in a memory space. Therefore it is applying a known technique (an entry associated with writes includes a length of the data and a compression state [0117], [0159] of Abe et al.) to a known device (a cache that logs changes/updates to a cache [0036] of Bazarsky et al.) ready for improvement to yield predictable results (a data length is stored as additional information for the entry [0117] of Abe et al.), KSR, MPEP 2143.
Claims 12 and 20 are rejected under 35 USC 103 for the same reasons as claim 1, as outlined above.
Allowable Subject Matter
Claims 2-11 and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Specifically regarding claim 2, “wherein the controller is configured to cause the apparatus to: identify the second logical address and the second physical address to write second data to a second block of the memory device; and determine whether the first logical address and the second logical address are sequential or nonsequential,” is not taught by the prior art of record. The closest prior art, Bazarsky et al. teaches updating of an L2P entry associated with a second logical address based on the received write command, however, is silent with regards to further determining whether the first and second logical addresses are sequential or non-sequential to each other as part of the modifying of the entry. Claims 3-7 would be allowable at least due to its dependency on claim 2.
Specifically regarding claim 8, “determine whether the first logical address associated with the first command matches the second logical address in the change log based at least in part on performing a search operation within the change log, wherein, to modify the entry associated with the change log, the controller is configured to cause the apparatus to: write information associated with the first command in a second entry in the change log, the second entry comprising a fourth field indicating an overlap between the entry and the second entry based at least in part on that the first logical address associated with the first command matches the second logical address in the change log,” is not taught by the prior art of record. While Bazarsky and Abe both teach modifying an existing entry in response to receiving the first command to write data, the prior art is silent with regards to further recording information into the change log that indicates whether or not there is an overlap between the entry and the second entry based on a matching of the logical addresses. Claims 9-11 would be allowable at least due to its dependency on claim 8.
Claim 13 recites substantially similar limitations as claim 2 and would therefore be allowable under the same rationale as claim 2. Claims 14-18 would be allowable at least due to its dependency on claim 13.
Claim 19 recites substantially similar limitations as claim 8 and would therefore be allowable under the same rationale as claim 8.
Response to Arguments
Applicant's arguments filed 1/7/2026 have been fully considered but they are not persuasive. It is argued, starting on page 11 and extending onto page 12 of the Remarks, that neither Bazarsky nor Abe teaches a third field indicating a compression state indicative of whether the entry is associated with one or more logical addresses written to one or more blocks of the memory device. Examiner respectfully disagrees. In regards to the compression function existence flag, Abe elaborates that information of each page, identified by a physical page number as well as the logical device ID and the logical address [0095], [0100], is stored as a record further including a compression function existence flag field. This compression function existence flag field stores information regarding whether the storage device in which the corresponding page exists has a compression function (where a state of 1 indicates there is a compression function and a state of 0 indicative that the storage device does not have a compression function [0099]). This teaching reads on the claimed features of a compression state indicative of whether the entry is associated with one or more logical addresses, as each page entry links a corresponding compression state with its physical and logical identifiers. Applicant’s arguments appear to generally allege that the cited references fail to teach the claim language (with bold facing and underlining for additional emphasis on certain terms) without specifically pointing out how the language of the claims patentably distinguishes them from the references. For example, Applicants state that the compression function existence flag of Abe is described as indicating whether a storage device is capable of performing a compression processing operation, which is not the same as, and does not teach or suggest “a compression state” on page 12 of the Remarks. It is unclear as to why the compression existence flag would not read on a compression state, unless Applicants suggest a specific meaning of the term “state” that is not yet claimed. For example, the instant specification discloses a compression indicator that is indicative of whether a entry has been back-merged with an original entry [0049], and Examiner notes that this specific teaching of compression state is not necessarily taught by the prior art of record.
Applicant is reminded of Allowable Subject Matter that was indicated in the previous action of 10/7/2025.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US 2023/0195646 A1) teaches a memory system may compress information associated with sequentially-index addresses and stored as a single, compressed entry.
Wang et al. (US 2022/0269407 A1) teaches a compressed size field which indicates the size of a given compressed data block that is associated with a corresponding LBA.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANE W BENNER whose telephone number is (571)270-0067. The examiner can normally be reached Mon - Thurs (8 AM - 5 PM).
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139