DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to amendment filed on 3/24/2026.
Claims 1, 16, and 19 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Interpretation
The examiner would like to note that the term duration is defined by independent claims 1, 16, and 19, “…the duration comprising a length to perform the first program operation.” Because duration is defined with open ended language, it can be interpreted as any length that contains the length to perform the first program operation, thus it can be significantly longer than only the length to perform the first program operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2012/0311244) and Lee et al. (US 2018/0005670).
With respect to claim 1, Huang teaches of an apparatus, comprising: a memory device (fig. 8, 11, 20; paragraph 100-101, 115, 136; flash memory device/memory system); and
a controller coupled with the memory device (fig. 8, 11, 20; paragraph 100-101, 115, 136; flash memory device controller), wherein the controller is configured to cause the apparatus to:
perform, at a first die of the apparatus during a duration, a first program operation as part of a transfer of first data from a source data block of the first die to a destination data block of the first die, the duration comprising a length to perform the first program operation (fig. 20-22; paragraphs 147-153; where the D1 to D3 folding occurs in 1 of the 3 dies in parallel which transfer the data from the binary section to the MLC section of each respective die. As the folding and writing operations are indicated as repeating, the claimed duration can be shown in the figures to be the length for one occurrence or even multiple occurrences of the folding the operations to occur);
receive, from a host system, a command to write second data to the apparatus during the duration (fig. 21-22; paragraph 100-101, 142, 146-147, 149; where the host issues a command to the memory to write data and the data is written to the RAM); and
perform, during the duration and based at least in part on the command, a write operation, that is concurrent with at least a portion of the first program operation, to write the second data to the apparatus and at least a portion of a second program operation as part of a transfer of third data from a source data block of the second die to a destination data block of the second die (fig. 20-22; paragraphs 139-140, 142, 147-153; where the host write data is written to the RAM and then to the binary section from the host. The write from the host to the RAM occurs in parallel with the foggy phase of the parallel folding process. The D1 to D3 folding occurs in a 2nd of the 3 dies in parallel which transfer the data from the binary section to the MLC section of each respective die).
Huang fails to explicitly teach of the write operation to write the second data to a second die of the apparatus.
However, Lee teaches of a multi-chip memory package that includes both flash dies and DRAM dies (fig. 2a; paragraph 29; where the MCP contains DRAM dies and NVM flash dies).
The combination of Huang and Lee teaches of perform, during the duration and based at least in part on the command, a write operation, that is concurrent with at least a portion of the first program operation, to write the second data to a second die of the apparatus (Huang, fig. 20-22; paragraphs 139-140, 142, 147-153; Lee, fig. 2a; paragraph 29; where in the combination as the RAM is on its own die, when the host write to RAM while the folding occurs in multiple flash dies in parallel, that write occurs in parallel to the RAM die).
Huang and Lee are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Huang and Lee before the time of the effective filing of the claimed invention to include the RAM of Huang being on a die as taught in Lee. Their motivation would have been to increase the flexibility of the memory system.
With respect to claim 16, the combination of Huang and Lee teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Huang also teaches of a non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to perform the steps of claim 1 (fig. 8; paragraphs 99-101; where the controllers contain software modules/components that are carried out by the controller to perform the operations).
With respect to claim 19, the combination of Huang and Lee teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
With respect to claim 2, 17, and 20, Huang teaches of wherein performing at least the portion of the second program operation is configured to cause the apparatus to: initiate, before receiving the command, the second program operation to program the second data to the destination data block of the second die (fig. 20-22; paragraphs 100-101, 147-153; where the D1 to D3 folding for each die occurs in parallel. As shown in fig. 22b, the host data written to the controller’s RAM from the commands occurs after the D1 to D3 folding begin);
suspend the second program operation based at least in part on initiating the write operation in response to receiving the command (fig. 21-22; paragraph 148-153; where the after the foggy phase of the folding occurs, the folding stops so that the host D1 write can occur); and
resume the second program operation after the write operation has been performed (fig. 21-22; paragraph 148-153; where after the host D1 write occurs, the fine phase of the folding is carried out).
With respect to claims 3 and 18, Huang teaches of wherein performing the write operation is configured to cause the apparatus to: perform the write operation while the second program operation is suspended (fig. 21-22; paragraph 148-153; where the host D1 write occurs after the foggy phase of the folding operation and before the fine phase of the folding operation).
With respect to claim 4, Huang teaches of wherein the controller is further configured to cause the apparatus to: track a status of the second program operation, wherein the second program operation is resumed based at least in part on tracking the status (fig. 21-22; paragraph 148-153; as the controller executes the host D1 write between the execution of the foggy and fine phases of the folding operations, the controller must know the status of what part of the folding operations are occurring).
With respect to claim 5, Huang teaches of wherein the second program operation is suspended and the write operation is performed based at least in part on a volatile memory device of the apparatus from which the second data is written being full (fig. 136, 150-152; the RAM is relatively small and will eventually fill up with data. Writes to the D1 memory need to occur to maintain memory operation. The RAM is filled up with 32 KB of host data and once 16 KB is transferred to the D1 memory, is has space to take in new data. Thus, the write to D1 memory (in between the foggy and fine folding phases) is carried out to release RAM space).
With respect to claim 6, Huang teaches of wherein the controller is further configured to cause the apparatus to: perform, at the second die during a second duration after the duration, a third program operation as part of a transfer of fourth data from the source data block of the second die to the destination data block of the second die, the second duration comprising a second length to perform the third program operation (fig. 21-22; paragraphs 147-153; where the D1 to D3 folding and host writing repeats. The folding occurs in the 2nd of the 3 dies in parallel which transfer the data from the binary section to the MLC section of each respective die. The claimed duration is shown in the figures as the length for the operations to occur);
receive, from the host system, a second command to write fifth data to the apparatus during the second duration (fig. 21-22; paragraph 100-101, 142, 146-147, 149; where the host issues another command to the memory to write data and the data is written to the RAM); and
perform, during the second duration and based at least in part on the second command, a second write operation to write the fifth data to the first die and at least a portion of a fourth program operation as part of a transfer of sixth data from the source data block of the first die to the destination data block of the first die (fig. 20-22; paragraphs 147-153; the writing is repeated and the host write data is written to the D1 after the foggy phase of the parallel folding process. The D1 to D3 folding occurs in the 1st of the 3 dies in parallel which transfer the data from the binary section to the MLC section of each respective die).
With respect to claim 7, Huang teaches of wherein the third program operation as part of the transfer of the fourth data corresponds to a second programming pass of the transfer of the third data (paragraph 136-138; where the folding transfers data from the binary section of memory to the MLC section (multi-programming pass)), and
the fourth program operation as part of the transfer of the sixth data corresponds to a second programming pass of the transfer of the first data (paragraph 136-138; where the folding transfers data from the binary section of memory to the MLC section (multi-programming pass)).
With respect to claim 8, Huang teaches of wherein performing at least the portion of the second program operation is configured to cause the apparatus to: initiate, during the duration, the second program operation (fig. 22; paragraph 152-153; where the folding is executed in parallel across multiple dies, thus the 2nd die’s folding is initiated at the same time the 1st die’s is);
determine, at one or more intervals during the duration, whether the command has been received (fig. 21-22; paragraph 100-101, 142, 146-147, 149; where the host issues commands to the memory to write data and the data is written to the RAM repeatedly during the folding operations); and
suspend the second program operation based at least in part on determining at an interval of the one or more intervals that the command has been received (fig. 20-22; paragraphs 147-153; where the host write data is written to the D1 after the foggy phase of the parallel folding process and before the fine phase).
With respect to claim 9, Huang teaches of wherein the controller is further configured to cause the apparatus to: receive, from the host system, a second command to write fourth data to the second die during the duration (fig. 21-22; paragraph 100-101, 142, 146-147, 149; where the host issues commands to the memory to write data and the data is written to the RAM repeatedly during the folding operations. As shown in fig. 22b; multiple writes of 16 KB of data are written to the RAM); and
perform a second write operation to write the fourth data to the apparatus during the duration based at least in part on temporarily suspending the second program operation in response to the second command (fig. 20-22; paragraphs 147-153; where the host write data is written to the D1 after the foggy phase of the parallel folding process and before the fine phase. As shown in fig. 22b; multiple writes of 16 KB of data are written to the D1 memory between the two folding phases).
With respect to claim 10, Huang teaches of wherein performing at least the portion of the second program operation is configured to cause the apparatus to: write the third data from the source data block of the second die to one or more latches of the apparatus (fig. 21; paragraph 148; where the x, y, and z pages are read into the data latches),
wherein performing the write operation comprises: overwrite the one or more latches with the second data based at least in part on receiving the command after the third data is written to the one or more latches (fig. 21; paragraph 148-149; where the data is loaded into the data latches and written to the D1 memory).
With respect to claim 11, Huang teaches of wherein performing at least the portion of the second program operation is configured to cause the apparatus to: rewrite, after the write operation is performed, the third data from the source data block of the second die to the one or more latches based at least in part on the overwriting (fig. 21; paragraph 148-149; where in the fine phase, the x, y, and z pages are again loaded into the latches); and
initiate a program of the third data to the destination data block of the second die from the one or more latches (fig. 21; paragraph 148-149; where in the fine phase, the x, y, and z pages are again loaded into the latches and programmed into the D3 memory).
With respect to claim 12, Huang teaches of wherein the command is received before a start time of the duration (fig. 21-22; paragraph 100-101, 147-153; whereas the folding and host writing cycle repeats, the host data is written to the controller RAM via the host command before a folding operation occurs).
With respect to claim 13, Huang teaches of wherein the command is received after a start time of the duration and during the duration (fig. 21-22b; paragraph 100-101, 147-153; whereas the folding and host writing cycle repeats, the host data is written to the controller RAM via the host command while a folding operation occurs).
With respect to claim 15, Huang teaches of wherein a second duration to perform the write operation is less than the duration (fig. 21-22; paragraph 147-153; where as shown in the figures, the host D1 write occurs in less time than the folding operations).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang and Lee as applied to claim 1 above and in further view of Venugopal et al. (US 2024/0221802).
With respect to claim 14, Huang teaches of wherein: the second data is written to single level cells, multi-level cells, or triple level cells of the second die (paragraph 88, 92, 115, 149; where the data from the host is written from the RAM to the D1 memory. D1 memory is binary or SLC memory).
The combination of Huang and Lee fails to explicitly teach of the destination data block of the first die and the destination data block of the second die comprise quad-level cells.
However, Venugopal teaches of the destination data block of the first die and the destination data block of the second die comprise quad-level cells (fig. 17; paragraph 147-148; where the folding operations are from an SLC memory to QLC memory).
Huang, Lee, and Venugopal are analogous art because they are from the same field of endeavor, as they are directed to memory.
It would have been obvious to one of ordinary skill in the art having the teachings of Huang, Lee, and Venugopal before the time of the effective filing of the claimed invention to fold the binary memory of the combination of Huang and Lee to QLC memory as taught in Venugopal. Their motivation would have been to more efficiently use the available memory space.
Response to Arguments
Applicant's arguments with respect to independent claims 1, 16, and 19 have been considered but are moot because of the new reference(s) being applied, in light of the amendment, to the particular limitations the arguments are referencing. Thereby the arguments no longer apply to the rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tran et al. (US 2014/0140138) discloses 3d flash memory that contains flash memory dies and RAM dies.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
/Michael Krofcheck/Primary Examiner, Art Unit 2138
Prosecution Insights