Prosecution Insights
Last updated: October 01, 2026
Application No. 18/954,337

DISPLAY PANEL

Non-Final OA §103
Filed
Nov 20, 2024
Priority
Apr 10, 2024 — TW 113113417
Examiner
BRIGGS, NATHANAEL R
Art Unit
Tech Center
Assignee
AUO Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
837 granted / 1098 resolved
+16.2% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
23 currently pending
Career history
1116
Total Applications
across all art units

Statute-Specific Performance

§103
59.2%
+19.2% vs TC avg
§102
32.2%
-7.8% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1098 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-3, 5-7 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (2021/0109389) in view of Huang et al. (US 2021/0325758). Regarding claim 1, Fan discloses a display panel (see figures 1-3, for instance), comprising: a first substrate (1000), having a first surface (facing 1004) and a second surface (S1000) opposite to the first surface; a first circuit structure ([0025]: “The active element array substrate 1000 may include a substrate (not shown), an active element array (not shown) disposed on the substrate, and peripheral circuits (not shown).”), disposed on the first surface of the first substrate; a second circuit structure (12), disposed on the second surface (S1000) of the first substrate (1000); a liquid crystal layer (1004), located on the first circuit structure ([0025]); a light-emitting diode module (LED module, 11), comprising: a flexible circuit board (13), connected to the second circuit structure (12), and bent (see figure 3, wherein 13 bends between 110 and 12) from the second surface (S1000) of the first substrate to above the first surface of the first substrate (at element 110); and a light-emitting diode (LED, 112R, G, B), disposed on the flexible circuit board (13) located above the first surface of the first substrate, and electrically connected to the flexible circuit board (13). However, Fan does not expressly disclose a sealant layer, surrounding the liquid crystal layer, and covering the LED; a second substrate, overlapping the first substrate, and the first circuit structure, the sealant layer, the liquid crystal layer and the LED are located between the first substrate and the second substrate. Huang discloses a display panel (see figure 3, for instance), comprising a sealant layer (114b), surrounding the liquid crystal layer (112), and covering the LED (118, analogous to LED portion of Fan); a second substrate (114a), overlapping the first substrate (1103), and the first circuit structure (on 110), the sealant layer (114b), the liquid crystal layer (112) and the LED (analogous to area at 118) are located between the first substrate (1103) and the second substrate (114a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the sealant and second substrate structure as Huang in the device of Fan, such that the liquid crystal layer and LEDs of Fan would be located alongside the sealant layer 114b of Huang between the first and second substrate. The motivation for doing so would have been to prevent water vapor from entering the device while increasing the water vapor battier capacity of the display device, as taught by Haung ([0025]). Regarding claim 2, Fan in view of Huang discloses the display panel of claim 1, further comprising: a plurality of LED modules (11A), wherein each of the plurality of LED modules comprises: a corresponding one flexible circuit board (13), connected to the second circuit structure (114), and bent from the second surface of the first substrate to the first surface of the first substrate (1000); and corresponding plurality of LEDs (112), disposed on the corresponding one flexible circuit board (13) located on the first surface of the first substrate, and electrically connected to the corresponding one flexible circuit board (see figure 3). Regarding claim 3, Fan in view of Huang discloses the display panel of claim 2, wherein each of the plurality of LED modules (11A) further comprises: a micro integrated circuit, bonded to the corresponding one flexible circuit board (13), wherein the second circuit structure comprises: a plurality of connection pads (114), bonded to the plurality of LED modules (11A); and a plurality of connection lines, each of the plurality of connection lines electrically connecting corresponding two adjacent ones of the plurality of LED modules ([0037]). Regarding claim 5, Fan in view of Huang discloses the display panel of claim 1, further comprising: an adhesive layer (Huang 118), located between the flexible circuit board (Fan 13) and the first surface of the first substrate (Fan 1000). Regarding claim 6, Fan in view of Huang discloses the display panel of claim 1, further comprising: a height augmentation layer (see Huang 113), located between the first substrate (Huang 1103) and the second substrate (Huang 114a), and overlapping the liquid crystal layer (Huang 112) in a normal direction of the first surface, wherein the height augmentation layer does not overlap the LED (Fan 112) in the normal direction of the first surface. Regarding claim 7, Fan in view of Huang discloses the display panel of claim 1, wherein the LED (112) is bonded to the flexible circuit board (113) through a conductive connection structure (114). Regarding claim 11, Fan in view of Huang discloses the display panel of claim 1, wherein the first circuit structure comprises a plurality of pixel structures (FR, FG FB), wherein the plurality of pixel structures overlap the liquid crystal layer (1004), and the LED module comprises a plurality of LEDs (112R, 112G, 112B), wherein a pitch between adjacent ones of the plurality of pixel structures is equal to a pitch between adjacent ones of the plurality of LEDs (see figure 3). Regarding claim 12, Fan in view of Huang discloses the display panel as of claim 1, further comprising: a first alignment mark (10020), disposed on the first surface of the first substrate (1000), and adjacent to a second alignment mark (region R2) in the LED module (112). Regarding claim 13, Fan in view of Huang discloses the display panel of claim 1, wherein part of the flexible circuit board (13) is located between the first substrate and the second substrate (since 13 extends from beneath 1000 to the top surface of 1002, portions of 13 is disposed between the first and second substrates). Regarding claim 14, Fan in view of Huang discloses the display panel of claim 1, wherein the first circuit structure ([0025]) further comprises: a first signal line, partially located between the flexible circuit board (13) and the first surface. Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fan in view of Huang, and in further view of Kao et al. (US 2019/0285953). Regarding claim 8, Fan in view of Huang discloses the display panel of claim 1. However, Fan in view of Huang does not expressly disclose wherein the first circuit structure comprises a plurality of first bonding pads and a plurality of pixel structures, wherein the plurality of pixel structures overlap the liquid crystal layer, and wherein a first system board is electrically connected to the plurality of first bonding pads, and electrically connected to the plurality of pixel structures through the plurality of first bonding pads. Kao discloses a display panel (see figures 1-2, for instance), wherein the first circuit structure comprises a plurality of first bonding pads (PA) and a plurality of pixel structures ([0024]), wherein the plurality of pixel structures ([0024]) overlap the liquid crystal layer (AR), and wherein a first system board ([0025]) is electrically connected to the plurality of first bonding pads (PA), and electrically connected (via DL) to the plurality of pixel structures through the plurality of first bonding pads. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the bonding pad structure of Kao in the device of Fan. The motivation for doing so would have been to optimize signal delivery in the device thereby enhancing display quality of the device, as taught by Kao ([0041]). Regarding claim 9, Fan in view of Huang and in further view of Kao discloses the display panel of claim 8, wherein the second circuit structure comprises: a plurality of second bonding pads (see figure 3 of Fan), wherein a second system board (12) is electrically connected to the plurality of second bonding pads, and the plurality of first bonding pads (114) and the plurality of second bonding pads (where 113 attaches to 12) are respectively located on the first surface and the second surface of the first substrate (1000); a plurality of connection pads (114), wherein the LED module (11A) is bonded to at least part of the plurality of connection pads (114); and a plurality of signal lines (on 13), electrically connecting the plurality of second bonding pads (where 13 connects to 12) and the plurality of connection pads (114). Allowable Subject Matter Claims 4 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANAEL R BRIGGS whose telephone number is (571)272-8992. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth can be reached at (571)-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHANAEL R BRIGGS/Primary Examiner, Art Unit 2871 8/27/2026
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Prosecution Timeline

Nov 20, 2024
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
88%
With Interview (+11.3%)
2y 7m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1098 resolved cases by this examiner. Grant probability derived from career allowance rate.

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