DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II in the reply filed on 18 February 2026 is acknowledged. The traversal is on the ground(s) that examination of all claims places no undue burden on the Examiner. This is not found persuasive because these species are different circuits, with different structures, connections, and components, requiring separate searches.
The requirement is still deemed proper and is therefore made FINAL.
Claims 6-10 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 18 February 2026.
Note that applicant indicated that claims 1-5, 8, and 10-20 read on the elected species. This does not appear to be accurate.
Besides claims 6 and 9, claims 8, 10, and 19 are also withdrawn.
In the case of claim 8, it recites that the dual gate transistor is arranged with its current conducting contacts between a second terminal of the LED and the second potential terminal. From this limitation the “second potential terminal” must be AVDD.
But it also recites that the charge storage is connected to the second control gate of the dual gate transistor as well as to the second potential terminal. But in Fig. 7 the charge storage is not connected to AVDD, but AVSS.
In the case of claim 10, it is dependent on claim 9.
In the case of claim 19:
It recites wherein a fifth control transistor is connected in parallel to the LED. This is the embodiment of Fig. 8.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 11-18, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1:
It recites “a LED pixel cell, in particular created with NMOS technology.” Does the pixel cell need to be created with NMOS technology, or not? This is ambiguous and therefore the metes and bounds of the claim are unclear.
Regarding claims 2-4, 11-18, and 21:
They are dependent on claim 1. Note that claim 20 specifically recites “wherein the transistors are field-effect transistors using NMOS technology.” This additional language makes the claim clear.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita et al. (US 2011/0122324)
Regarding claim 1:
Yamashita discloses:
Device for the electronic control of a LED pixel cell (Fig. 6), in particular created with NMOS technology (paragraph 78), comprising:
a data signal line (Fig. 6: DTL), a threshold signal line (Fig. 63: BGL; where this is used to control the threshold voltage correction as per paragraph 85) and a selection signal line (Fig. 6: WSL);
an LED (Fig. 6: 11) electrically connected in series with a dual-gate transistor (Fig. 6: Tr3) and together with the latter between a first and a second potential terminal (Vcc and GND);
wherein the dual-gate transistor is arranged with its current line contacts between a terminal of the LED and one of the potential terminals (Tr3 is between Vcc and 11), and a first control gate of the dual-gate transistor is connected to the threshold line (G4);
a selection hold circuit having a charge storage (Fig. 6: Cs) coupled to a second control gate of the dual gate transistor (it is connected to G1) and to a current line contact of the dual gate transistor (it is connected at Vs which is in the current line of the transistor G4), and a control transistor having its control terminal connected to the select signal line (Fig.6: Tr3).
Regarding claim 2:
Yamashita discloses:
wherein the dual gate transistor comprises a back gate transistor, in which the back gate forms the first control gate (as seen in Fig. 6).
Regarding claim 3:
Yamashita discloses:
wherein the first control gate of the dual-gate transistor is designed to set a threshold voltage (paragraph 85).
Regarding claim 4:
Yamashita discloses:
wherein the dual-gate transistor comprises a thin-film transistor with two opposing control gates (paragraph 79).
Regarding claim 20:
Yamashita discloses:
wherein the transistors are field-effect transistors using NMOS technology (paragraph 79).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Sarma (US 2006/0164345)
Regarding claim 5:
Yamashita discloses a device as discussed above.
Yamashita does not disclose:
“a switching signal (PWM signal) is applied to the threshold line during operation.”
Sarma discloses:
a switching signal (PWM signal) is applied to the threshold line during operation (paragraph 41).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Yamashita wherein a switching signal (PWM signal) is applied to the threshold line during operation, as suggested by Sarma
The rationale is as follows:
Yamashita and Sarma are directed to the same field of art.
Sarma applied a PWM signal through an additional transistor (Fig. 6: T3), but there is no need for this in Yamashita because the driving transitor already has a second gate. Sarma discloses this can reduce flicker (paragraph 41). This is a known improvement that one of ordinary skill in the art could have included with predictable results.
Regarding claim 21:
Yamashita in view of Sarma discloses:
wherein an analog data drive signal for color control of the LED is applied to the LED via the selection hold circuit by means of the selection signal (this is the data signal on line DTL of Yamashita Fig. 6, which can be seen is controlled by the selection line WSL via the transistor Tr4), and brightness control of the LED is effected by means of a coupled-in pulse width modulation signal (taught by Sarma as discussed above).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 11-18, and 20-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 6-8, 15-18, and 20 of U.S. Patent No. 12,205,521. Although the claims at issue are not identical, they are not patentably distinct from each other as follows.
Regarding claim 1:
Patent claim 1 discloses every element of the instant claim 1 as follows.
Instant Application
Patent 12,205,521
1. Device for the electronic control of a LED pixel cell, in particular created with NMOS technology, comprising:
1. A device for electronic control of a μ-LED pixel cell, comprising:
a data signal line, a threshold signal line and a selection signal line;
a data signal line, a threshold line configured to receive a pulse width modulation (PWM) signal as a switching signal during operation, and a selection signal line;
an LED electrically connected in series with a dual-gate transistor and together with the latter between a first and a second potential terminal;
a μ-LED electrically connected in series to a dual-gate transistor and together with it between a first and second potential terminal; wherein
wherein the dual-gate transistor is arranged with its current line contacts between a terminal of the LED and one of the potential terminals, and a first control gate of the dual-gate transistor is connected to the threshold line;
the dual-gate transistor is arranged with its current conduction contacts between a terminal of the μ-LED and a potential terminal, and a first control gate of the dual-gate transistor is connected to the threshold line; and
a selection hold circuit having a charge storage coupled to a second control gate of the dual gate transistor and to a current line contact of the dual gate transistor, and a control transistor having its control terminal connected to the select signal line.
a selection hold circuit comprising a capacitor coupled to a second control gate of the dual-gate transistor and to a current conduction contact of the dual-gate transistor, and a control transistor having its control terminal connected to the selection signal line;
wherein a first charge storage is connected to the second control gate of the dual-gate transistor and to the first potential terminal; and
wherein the device further comprises a temperature compensation circuit with a negative feedback based on detection of a forward voltage by the μ-LED, the temperature compensation circuit being configured on an output side to output a signal on the threshold line.
Regarding claims 2-4:
Patent claims 2-4 disclose these additional elements.
Regarding claim 5:
Patent claim 1 discloses the PWM signal.
Regarding claim 11:
These additional elements are in patent claim 1.
Regarding claims 12-14:
These additional elements are in patent claims 6-8.
Regarding claims 15-18:
These elements are in patent claims 9-12.
Regarding claim 20:
These elements are in patent claim 13.
Regarding claim 21:
This is a claim to the method of operating the circuit of claim 1. Although the patent did not have a method claim, the method follows from the recited structure of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Minami et al. (US 2012/0327058); Takizawa et al. (US 2017/0025061); Zhang (US 2019/0005882).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER RAY LAMB whose telephone number is (571)272-5264. The examiner can normally be reached 8:30-5:00 PM.
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/CHRISTOPHER R LAMB/Primary Examiner, Art Unit 2622