Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 07/22/2026. Claims 1 and 16 have been amended. Claims 1-16 are pending on this application.
Response to Arguments
3. Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-3, 8 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai Pub. No. 2018/0175875.
Regarding claim 1. Fig. 3a of Tsai discloses passive noise-shaping (Cr) successive-approximation analog-to-digital converter (paragraph 0042) comprising: a SAR ADC circuit (Fig. 3a), configured to perform conversion upon an analog input signal (V) and extract residue (Vr) at an end of the conversion (conversion of W3); and a passive noise-shaping circuit (Cr), configured to process the residue (Vr) and feed a processed residue back (Vr) to the SAR ADC circuit (Fig. 3a) , wherein the passive noise-shaping circuit (Vr) comprises: at least one passive element with tunable capacitance (Variable Cr) , configured to perform residue amplification (Vr amplification of Cr) , wherein the residue amplification (Vr amplification of Cr) is performed by changing the tunable capacitance (var_c) from one capacitance value (capacitor value of Cr) to another capacitance value (another capacitor value of Cr).
Regarding claim 2. The passive noise-shaping SAR ADC of claim 1, Fig. 3a further discloses wherein the SAR ADC circuit (Fig. 3a) comprises: a first capacitor digital-to-analog converter (switching capacitor Cs); and a comparator (320) , having an inverting input terminal and a non-inverting input terminal (- /+ input of 320) ; and the passive noise-shaping circuit (Cr.; see Fig. 9b for discloses diagram of variable capacitor Cr) comprises: a first capacitor (C[1] in Fig. 9b), wherein the first capacitor (C[1] in Fig. 9b) is a tunable capacitor tunable (tunable by switch of C[1] in Fig. 9b) ; a second capacitor (C[j-1] in Fig. 9b); a third capacitor (C[j] in Fig. 9b) ; and a switch circuit (Sr3) , configured to control charge sharing between the first CDAC (switching capacitor Cs) and the first capacitor (C[1] in Fig. 9b) , charge sharing between the first capacitor (C[1] in Fig. 9b) and one of the second capacitor ((C[j-1] in Fig. 9b) and the third capacitor ((C[j] in Fig. 9b), connection of another of the second capacitor (C[j-1] in Fig. 9b) and the third capacitor ((C[j] in Fig. 9b) between the first CDAC (switching capacitor Cs) and the comparator (320 ), and capacitor swapping (swapping of capacitor of Fig. 9a) between the second capacitor ((C[j-1] in Fig. 9b) and the third capacitor (C[j] in Fig. 9b) .
Regarding claim 3. The passive noise-shaping SAR ADC of claim 2, Fig. 3a and Fig. 9b further discloses wherein the first capacitor (C[1] in Fig. 9b) has a first capacitance value (greater capacitor of C[1]) during a first period (period of bottom of C1 connected to ground in Fig. 9b) in which the switch circuit (Sr3) enables the charge sharing between the first CDAC (Switching capacitor Cs) and the first capacitor (C[1] in Fig. 9b), and has a second capacitance value (less capacitance in Fig. 9b) during a second period (period of bottom capacitor C[1] connected to top plate of second capacitor C[j-1] in Fig. 9b) in which the switch circuit enables the charge sharing between the first capacitor ((C[1] in Fig. 9b) and said one of the second capacitor (C[j-1] in Fig. 9b) and the third capacitor (C[j] in Fig. 9b) , where the first period (greater capacitance period in Fig. 9b) and the second period (lesser capacitance perior) are non-overlapping periods (non-overlapping of greater capacitance period and lesser capacitance period in Fig. 9b), and the first capacitance value is larger (greater capacitance in Fig. 9b) than the second capacitance value (lesser capacitance in Fig. 9b).
Regarding claim 8. The passive noise-shaping SAR ADC of claim 2, Fig. 3a and Fig. 9b further discloses wherein when the passive noise-shaping SAR ADC (Fig. 3a) operates in a capacitor swapping phase (swapping between greater capacitance and lesser capacitance in Fig. 9b) , the switch circuit (Sr3) disconnects the first capacitor (C[1] in Fig. 9b) from an output terminal of the first CDAC (output terminal of Cs) and said one of the second capacitor (C[j-1] in Fig. 9b) and the third capacitor (C[j] in Fig. 9b), and swaps the second capacitor (C[j-1] in Fig. 9b) and the third capacitor (C[j]).
Regarding clam 16. Fig. 3a of Tsai discloses an analog-to-digital conversion method comprising: performing successive-approximation analog-to-digital conversion (paragraph 0042) upon an analog input signal (V) ; extracting residue (Vr) at an end (conversion of W3) of the successive-approximation analog-to-digital conversion (paragraph 0042); and using only passive elements (Variable capacitor Vr) to process the residue (Vr) and feed a processed residue (Vr) back to the successive-approximation analog-to-digital conversion (Fig. 3a) for noise-shaping (paragraph 0002) , comprising: performing residue amplification (Vr amplification) through at least one passive element (Cr) with tunable capacitance (tunable capacitance of Cr) , wherein the residue amplification (Vr amplification) is performed by changing the tunable capacitance (tunable capacitance of Cr) from one capacitance value (capacitance value of Cr) to another capacitance value (another capacitance of Cr).
Allowable Subject Matter
6. Claim 4 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein when the passive noise-shaping SAR ADC operates in a sample phase, the switch circuit disconnects the first capacitor from an output terminal of the first CDAC and said one of the second capacitor and the third capacitor, connects said one of the second capacitor and the third capacitor to the output terminal of the first CDAC, and connects said another of the second capacitor and the third capacitor between the output terminal of the first CDAC and one of the inverting input terminal and the non-inverting input terminal of the comparator.
7. Claim 5 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein when the passive noise-shaping SAR ADC operates in a conversion phase, the switch circuit disconnects the first capacitor from an output terminal of the first CDAC and said one of the second capacitor and the third capacitor, connects said one of the second capacitor and the third capacitor to the output terminal of the first CDAC, and connects said another of the second capacitor and the third capacitor between the output terminal of the first CDAC and one of the inverting input terminal and the non-inverting input terminal of the comparator.
8. Claim 6 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein when the passive noise-shaping SAR ADC operates in a residue collection phase, the first capacitor is controlled to increase its capacitance value, and the switch circuit connects the first capacitor to an output terminal of the first CDAC, disconnects the first capacitor from said one of the second capacitor and the third capacitor, disconnects said one of the second capacitor and the third capacitor from the output terminal of the first CDAC, and connects said another of the second capacitor and the third capacitor between the output terminal of the first CDAC and one of the inverting input terminal and the non-inverting input terminal of the comparator.
9. Claim 7 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein when the passive noise-shaping SAR ADC operates in a residue boost phase, the first capacitor is controlled to decrease its capacitance value, and the switch circuit disconnects the first capacitor from an output terminal of the first CDAC, connects the first capacitor to said one of the second capacitor and the third capacitor, disconnects said one of the second capacitor and the third capacitor from the output terminal of the first CDAC, and connects said another of the second capacitor and the third capacitor between the output terminal of the first CDAC and one of the inverting input terminal and the non-inverting input terminal of the comparator.
10. Claims 9-15 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the analog input signal is a differential signal, and the SAR ADC circuit further comprises: a second CDAC; and the passive noise-shaping circuit further comprises: a fourth capacitor, wherein the fourth capacitor is a tunable capacitor; a fifth capacitor; and a sixth capacitor; wherein the switch circuit is further configured to control charge sharing between the second CDAC and the fourth capacitor, charge sharing between the fourth capacitor and one of the fifth capacitor and the sixth capacitor, charge sharing between the first capacitor and said one of the fifth capacitor and the sixth capacitor, charge sharing between the fourth capacitor and said one of the second capacitor and the third capacitor, connection of another of the fifth capacitor and the sixth capacitor between the second CDAC and the comparator, and capacitor swapping between the fifth capacitor and the sixth capacitor.
Conclusion
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
09/09/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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