DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 04/06/2026. Claims 5 and 15 have been amended.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. [US 2015/0324137 A1].
Regarding claim 1, Wu teaches “A device, comprising:” as “ a plurality of applications are pre-loaded in volatile memory in the computing device until it is determined that available space in the volatile memory has dropped below a threshold level.” [¶0003]
“a first memory to store a data;” as “FIG. 1 is a block diagram of a computing device 100 of an embodiment. As shown in FIG. 1, the computing device 100 comprises a processor 110, non-volatile memory 120, volatile memory 130 (e.g., RAM)” [¶0038] (A processor, a volatile memory and a non-volatile storage is in the structure)
“a controller to manage the first memory;” as “The controller of the storage module receives a multi-block erase command from the processor of the computing device to erase the plurality of blocks in the swap area in non-volatile memory ” [¶0006] (storage controller receives commands configuring part of the non-volatile memory as swap memory—i.e., a request to use the memory as a memory device by erasing it.)
“a storage media to store a copy of the data; and” as [Fig. 2, element 220] (The non-volatile memory 220 stored the data)
“a module to support page swapping with a second memory associated with a processor.” as “The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. ” [¶0036] (Wu directly teaches use of a non-volatile memory swap area as an extension to volatile memory.)
Regarding claim 3, Wu teaches “wherein the first memory is configured to store a page table associated with the second memory.” as “ The swapping mechanism is initiated as part of the system boot process. The initiation process includes cleaning the swap partition by erasing the content of the partition, either through a pseudo erase which only modifies the mapping table or actual overwrite of the data for security purposes. ” [¶0089]
Regarding claim 4, Wu teaches “wherein the first memory is configured to store page tracking data.” as “ in one alternative, the processor 110 can monitor for all I/O utilization” [¶0079]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. [US 2015/0324137 A1] in view of Pedawi [US 2018/0350021 A1].
Claim 2 is rejected over Wu and Pedawi.
Wu does not explicitly teach wherein the module includes at least one of a compression/decompression unit, and encryption/decryption unit, a page selection module to select pages to move pages between the first memory and the second memory, and a preload engine.
However, Pedawi teaches “wherein the module includes at least one of a compression/decompression unit, and encryption/decryption unit, a page selection module to select pages to move pages between the first memory and the second memory, and a preload engine.” as “ At step 712, the system converts the input text string, error correction code words, a character count indicator, any padding bits, and/or any encryption keys into 8-bit code words and further assigns the 8-bit code words into blocks of data.” [¶0091] and “The resulting global address QR code includes the encoded text input strings that can be decoded without the aid or the internet or another data network.” [¶0095]
Wu and Pedawi are analogous arts because they teach storage system architecture and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Wu and Pedawi before him/her, to modify the teachings of Wu to include the teachings of Pedawi with the motivation of LZ optimized for decompression speed and compression ratio. [Pedawi, ¶0070]
Claim(s) 5-8 and 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. [US 2015/0324137 A1] in view of Hyvonen et al. [US 11,494,080 B2].
Claim 5 is rejected over Wu and Hyvonen.
Wu teaches “A method, comprising:” as “a method and computing device are disclosed for using both volatile memory and non-volatile swap memory to pre-load a plurality of applications.” [¶0003]
“exposing, by a device, the device to a processor, the device including a first memory and a storage media;” as “FIG. 1 is a block diagram of a computing device 100 of an embodiment. As shown in FIG. 1, the computing device 100 comprises a processor 110, non-volatile memory 120, volatile memory 130 (e.g., RAM)” [¶0038] (A processor, a volatile memory and a non-volatile storage is in the structure)
“receiving, at the device, a first request to use the memory of the device as a memory device;” as “The controller of the storage module receives a multi-block erase command from the processor of the computing device to erase the plurality of blocks in the swap area in non-volatile memory ” [¶0006] (storage controller receives commands configuring part of the non-volatile memory as swap memory—i.e., a request to use the memory as a memory device by erasing it.)
“wherein the processor uses the memory device as a swap space for the second memory, and” as “The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. ” [¶0036] (Wu directly teaches use of a non-volatile memory swap area as an extension to volatile memory.)
Wu does not explicitly teach configuring, by the device, the device to operate as an extension of a second memory associated with the processor;
receiving, at the device from the processor, a second request for a data in the device; and
wherein the second memory is external to the device.
However, Hyvonen teaches “configuring, by the device, the device to operate as an extension of a second memory associated with the processor;” as “The system comprises a host for issuing one or more commands in accordance with access needs for the memory device, and an entity for receiving the commands and configuring access to the memory device in accordance with at least one or more access profiles.” [Col 3, lines 15-20] (The citation describes receiving one or more commands that activate specific access profiles for the memory device.)
“receiving, at the device from the processor, a second request for a data in the device; and” as “Since the system that accesses the memory device knows, or is capable of determining, the type of memory access needs (e.g., whether it is a read, write, erase, modify attribute, random, or a sequential operation), it can issue commands for configuring the memory device in accordance with an access profile that is most optimized/suitable for the particular access command. ” [Col 3, lines 60-67] (The citation describes host-issued commands (read/write/modify) received by the memory device controller.)
“processing, by the device, the second request,” as “the memory device firmware may take an action in accordance with the access profile request of an embodiment of the present invention and handle the 110 operation in a different way.” [Col 8, lines 23-26] (The art teaches the controller processes host commands to access or modify memory.)
“wherein the second memory is external to the device.” as “this need may arise when the system is connected to an external mass storage device.” [Col 6, lines 14-16]
Wu and Hyvonen are analogous arts because they teach storage system architecture and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Wu and Hyvonen before him/her, to modify the teachings of Wu to include the teachings of Hyvonen with the motivation of it may be advantageous to conduct two or more memory access operations in parallel. [Hyvonen, Col 6, lines 45-46]
Claim 6 is rejected over Wu and Hyvonen.
Wu teaches “wherein configuring, by the device, the device to operate as the extension of the second memory associated with the processor includes configuring, by the device, a first portion of the first memory to operate as the extension of the second memory.” as “the processor 110 can use the non-volatile memory 120 as a memory extension to the storage space in the volatile memory 130, and move (or “swap out”) the application data from the volatile memory 130 to the non-volatile memory 120.” [¶0052]
Claim 7 is rejected over Wu and Hyvonen.
Wu teaches “further comprising executing, by the device, an algorithm to select the data to swap between the first memory and the second memory.” as “a best-fit algorithm can be used to determine the most-efficient methodology to pre-load the applications, and most-recently-used application and user-preference algorithms can be used as pre-loading factors.” [¶0070]
Claim 8 is rejected over Wu and Hyvonen.
Wu teaches “receiving, at the device from the processor, the second request for the data in the device includes receiving, at the device from the processor, a read request, the read request including an address; and” as “The application management layer 305 requests a service from the operating system kernel 310 by issuing function calls, such as, for example, close, open, read, wait, and write calls.” [¶0045]
“processing, by the device, the second request includes:” as “User experience is proportional to the performance of the read command” [¶0072]
“reading, by the device, the data from the first memory based at least in part on the address; and” as “the longer a read command takes to complete, the longer the delay felt by the user. ” [¶0072]
“sending, from the device to the processor, the data to the second memory.” as “The amount of memory swapped out is directly proportional to the memory demand, and, in times of severe memory shortage, large chunks of memory will be swapped out over a short period of time.” [¶0072]
Claim 12 is rejected over Wu and Hyvonen.
Wu teaches “receiving, at the device from the processor, the second request for the data in the device includes receiving, at the device from the processor, a preload request, the preload request identifying at least a second data; and” as “different techniques can be used to determine the application preload sequence, determine when to preload applications (e.g. to avoid preloading when the computing device 100 is in its critical loading process, as this can slow down boot up), dynamically manage free, cached, and swap memory, and automatically terminate specific applications during the time of critical memory allocation.” [¶0070]
Wu does not explicitly teach processing, by the device, the second request includes:
reading, by the device, the second data from the storage media; and
storing, by the device, the second data in the first memory.
However, Hyvonen teaches “processing, by the device, the second request includes:” as “the memory device firmware may take an action in accordance with the access profile request of an embodiment of the present invention and handle the 110 operation in a different way.” [Col 8, lines 23-26]
“reading, by the device, the second data from the storage media; and” as “The exemplary default profile used in FIG. 3 configures the memory device to accommodate the reading of large sequential data from the memory device.” [Col 6, lines 1-5]
“storing, by the device, the second data in the first memory.” as “user data, and other parameters may be stored on the same device.” [Col 4, lines 37-38]
Claim 13 is rejected over Wu and Hyvonen.
Wu teaches “the first memory is configured to store a page table associated with the second memory;” as “The swapping mechanism is initiated as part of the system boot process. The initiation process includes cleaning the swap partition by erasing the content of the partition, either through a pseudo erase which only modifies the mapping table or actual overwrite of the data for security purposes. ” [¶0089]
“receiving, at the device from the processor, the second request for the data in the device includes receiving, at the device from the processor, a request for an entry in a page table; and” as “As NAND internally remaps the logical address, a special command is needed to force an actual erase of the used NAND blocks. ” [¶0089]
Wu does not explicitly teach processing, by the device, the second request includes: identifying, by the device, the entry in the page table stored in the first memory; and
sending, from the device to the processor, the entry in the page table stored in the first memory.
However, Hyvonen teaches “processing, by the device, the second request includes: identifying, by the device, the entry in the page table stored in the first memory; and” as “The system comprises an entity for receiving one or more commands for activating one or more access types associated with the memory device,” [Col 3, lines 9-12]
“sending, from the device to the processor, the entry in the page table stored in the first memory.” as “ the mapping may be directed to a more a more durable and performance-effective portion of the physical memory, a portion of the memory that utilizes a specific memory technology, or to a separate physical chip that is more suitably designed for such repeated access operations. ” [Col 8, lines 18-22]
Claim 14 is rejected over Wu and Hyvonen.
Wu teaches “the first memory is configured to store a page tracking data;” as “in one alternative, the processor 110 can monitor for all I/O utilization” [¶0079]
“receiving, at the device from the processor, the second request for the data in the device includes receiving, at the device from the processor, an update request for the page tracking data; and” as “The host controller 110 updates the flash translation layer (FTL) in the storage device controller with the erased blocks.” [¶0091]
“processing, by the device, the second request includes updating the page tracking data based at least in part on the update request.” as “Depending on the FTL design, the memory device may do a background erase or hold the blocks until needed. The host controller 110 then sends the write commands to the memory (act 2620). ” [¶0091]
Claim 15 is rejected over Wu and Hyvonen.
Wu teaches “A method, comprising:” as “a method and computing device are disclosed for using both volatile memory and non-volatile swap memory to pre-load a plurality of applications.” [¶0003]
“exposing, by a device, the device to a processor, the device including a first memory and a storage media;” as “receiving, at a processor, a notification that a device is available, the device including a first memory and a storage media;” [¶0038] (A processor, a volatile memory and a non-volatile storage is in the structure)
“sending, from the processor to the device, a first request for the device to configure itself as a memory device; and” as “The controller of the storage module receives a multi-block erase command from the processor of the computing device to erase the plurality of blocks in the swap area in non-volatile memory ” [¶0006] (storage controller receives commands configuring part of the non-volatile memory as swap memory—i.e., a request to use the memory as a memory device by erasing it.)
“and wherein the processor uses the disk as a swap space for a second memory associated with the processor, and” as “The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. ” [¶0036] (Wu directly teaches use of a non-volatile memory swap area as an extension to volatile memory.)
Wu does not explicitly teach sending, from the processor to the device, a second request for a data in the memory device,
wherein the second memory is external to the device.
However, Hyvonen teaches “sending, from the processor to the device, a second request for a data in the memory device,” as “Since the system that accesses the memory device knows, or is capable of determining, the type of memory access needs (e.g., whether it is a read, write, erase, modify attribute, random, or a sequential operation), it can issue commands for configuring the memory device in accordance with an access profile that is most optimized/suitable for the particular access command.” [Col 3, lines 60-67] (The citation describes host-issued commands (read/write/modify) received by the memory device controller.)
“wherein the second memory is external to the device.” as “this need may arise when the system is connected to an external mass storage device.” [Col 6, lines 14-16]
Wu and Hyvonen are analogous arts because they teach storage system architecture and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Wu and Hyvonen before him/her, to modify the teachings of Wu to include the teachings of Hyvonen with the motivation of it may be advantageous to conduct two or more memory access operations in parallel. [Hyvonen, Col 6, lines 45-46]
Claim 16 is rejected over Wu and Hyvonen.
Wu teaches “further comprising reserving the device for use by the processor.” as “and allocates memory for the application data (act 820).” [¶0068]
Claim 17 is rejected over Wu and Hyvonen.
Wu teaches “sending, from the processor to the device, the first request for the device to configure itself as the memory device includes sending, from the processor to the device, the first request for the device to configure a first portion of the first memory as the memory device; and the method further comprises exposing, by the processor, the second portion of the first memory to an application executing on the processor.” as “In FIG. 4A, the volatile memory (DDR) 130 stores the application code and application data for Apps 2 through n+1.” [¶0054]
Claim 18 is rejected over Wu and Hyvonen.
Wu teaches “wherein sending, from the processor to the device, a second request for a data in the memory device includes sending, from the processor to the device, a preload request, the preload request identifying at least a second data.” as “different techniques can be used to determine the application preload sequence, determine when to preload applications (e.g. to avoid preloading when the computing device 100 is in its critical loading process, as this can slow down boot up), dynamically manage free, cached, and swap memory, and automatically terminate specific applications during the time of critical memory allocation.” [¶0070]
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. [US 2015/0324137 A1] in view of Hyvonen et al. [US 11,494,080 B2] and in further view of Pedawi [US 2018/0350021 A1].
Claim 9 is rejected over Wu, Hyvonen and Padawi.
The combination of Wu, Hyvonen does not explicitly teach reading, by the device, the data from the first memory based at least in part on the address includes reading, by the device, a compressed data from the first memory based at least in part on the address; and
processing, by the device, the second request further includes decompressing, by the device, the compressed data to produce the data.
However, Pedawi teaches “reading, by the device, the data from the first memory based at least in part on the address includes reading, by the device, a compressed data from the first memory based at least in part on the address; and” as “ the route information may be compressed so the information encoded uses fewer bits than the original representation of the data.” [¶0069]
“processing, by the device, the second request further includes decompressing, by the device, the compressed data to produce the data.” as “other LZ methods that use a table-based compression model where table entries are substituted for repeated strings of data.” [¶0070]
Wu, Hyvonen and Padawi are analogous arts because they teach storage system architecture and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Wu, Hyvonen and Padawi before him/her, to modify the teachings of combination of Wu, Hyvonen to include the teachings of Pedawi with the motivation of LZ optimized for decompression speed and compression ratio. [Pedawi, ¶0070]
Claim 10 is rejected over Wu, Hyvonen and Padawi.
The combination of Wu, Hyvonen does not explicitly teach reading, by the device, the data from the first memory based at least in part on the address includes reading, by the device, an encrypted data from the first memory based at least in part on the address; and
processing, by the device, the second request further includes decrypting, by the device, the encrypted data to produce the data.
However, Pedawi teaches “reading, by the device, the data from the first memory based at least in part on the address includes reading, by the device, an encrypted data from the first memory based at least in part on the address; and” as “ At step 712, the system converts the input text string, error correction code words, a character count indicator, any padding bits, and/or any encryption keys into 8-bit code words and further assigns the 8-bit code words into blocks of data.” [¶0091]
“processing, by the device, the second request further includes decrypting, by the device, the encrypted data to produce the data.” as “The resulting global address QR code includes the encoded text input strings that can be decoded without the aid or the internet or another data network.” [¶0095]
Wu, Hyvonen and Padawi are analogous arts because they teach storage system architecture and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Wu, Hyvonen and Padawi before him/her, to modify the teachings of combination of Wu, Hyvonen to include the teachings of Pedawi with the motivation of LZ optimized for decompression speed and compression ratio. [Pedawi, ¶0070]
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. [US 2015/0324137 A1] in view of Hyvonen et al. [US 11,494,080 B2] and in further view of Greathouse et al. [US 2015/0206574 A1].
Claim 11 is rejected over Wu, Hyvonen and Greathouse.
The combination of Wu, Hyvonen does not explicitly teach wherein sending, from the device to the processor, the data to the second memory includes executing, by the device, a direct memory access (DMA) command to write the data to the second memory.
However, Greathouse teaches “wherein sending, from the device to the processor, the data to the second memory includes executing, by the device, a direct memory access (DMA) command to write the data to the second memory.” as “The processing system 100 shown in FIG. 1 also includes direct memory access (DMA) logic 120 for generating addresses and initiating memory read or write cycles. ” [¶0015]
Wu, Hyvonen and Greathouse are analogous arts because they teach storage system architecture and memory management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Wu, Hyvonen and Greathouse before him/her, to modify the teachings of combination of Wu, Hyvonen to include the teachings of Greathouse with the motivation of swapping the data from the DRAM lines with higher refresh rates to the non-volatile memory allows the memory system to reduce the overall refresh rate of the DRAM without sacrificing data integrity or performance, thereby conserving power and increasing memory utilization for useful data transfers as opposed to refresh activities.. [Greathouse, ¶0012]
Response to Arguments
Applicant's arguments filed on 04/06/2026 have been fully considered but they are not persuasive.
Regarding claim 1, applicant contends that Wu fails to disclose distinct memory elements, a controller managing the first memory, and a storage media.
This argument is not persuasive. Wu discloses a computing device including volatile memory and non-volatile memory (Wu ¶38), where the non-volatile memory stores data and functions as swap space, thereby meeting the claimed “storage media.” The claim does not require physical separation of these elements. Further, Wu discloses a controller managing memory operations (Wu ¶6), which reasonably corresponds to the claimed controller. Accordingly, Wu teaches all limitations of claim 1.
Regarding claim 3, applicant argues that Wu does not disclose a page table.
This argument is not persuasive. Wu discloses a mapping table used for memory management (Wu ¶89), which corresponds to a page table. The fact that the table is modified or cleared during initialization does not negate its presence or use.
Regarding claim 4, applicant argues that I/O utilization is not page tracking data.
This argument is not persuasive. Wu discloses monitoring I/O utilization to control memory operations (Wu ¶79), which constitutes tracking of memory-related data. The claim does not limit the type of tracking data, and thus broadly encompasses such metrics.
Regarding claim 2, applicant argues Pedawi does not teach compression/decompression or encryption/decryption.
This argument is not persuasive. Pedawi discloses encoding and decoding of data into structured code words (Pedawi ¶91, ¶95), which reasonably correspond to compression/decompression and encryption/decryption functions. It would have been obvious to incorporate such data processing techniques into Wu to improve data handling efficiency.
Applicant further presents various arguments that Wu does not disclose exposing the device to a processor, configuring memory as an extension, or processing requests.
These arguments are not persuasive. Wu discloses interaction between a processor and memory device and explicitly teaches using non-volatile memory as a swap space and extension of volatile memory (Wu ¶36, ¶52). Hyvonen further teaches receiving and processing memory access commands and configuring memory operation based on such commands (Hyvonen col. 3, lines 15–20, 60–67).
Regarding claim 7 Wu discloses use of algorithms (e.g., best-fit, LRU) to determine memory operations (Wu ¶70).
Regarding claim 8 Wu discloses read/write operations and data access based on requests (Wu ¶45, ¶72).
Regarding claim 12 Wu discloses preloading operations identifying data to be loaded (Wu ¶70).
Regarding claims 13 and 19 Wu’s mapping table (¶89), in view of Hyvonen’s command-response framework, renders retrieval and transmission of entries obvious.
Regarding claims 14 and 20 Wu discloses updating memory management structures (e.g., FTL updates) (Wu ¶91), which corresponds to tracking and updating memory-related data.
Regarding claims 9–10 applicant’s arguments on Pedawi are not persuasive for the reasons discussed above. Pedawi’s encoding/decoding operations correspond to compression and encryption functions, and their incorporation into the combined system would have been obvious.
Regarding claim 11, Applicant argues that Greathouse does not teach DMA as claimed.
This argument is not persuasive. Greathouse discloses DMA operations for transferring data between memory components (Greathouse ¶15). Incorporating DMA functionality into the memory system of Wu and Hyvonen would have been an obvious design choice to improve transfer efficiency.
The rejections of claims 1–18 are therefore maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
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