DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 line 4 “switchs” appears to be a typographical error and applicant intended to use the term -- switches--.
Claim 1 line 9 “switchs” appears to be a typographical error and applicant intended to use the term -- switches--.
Claim 1 line 21 “antoher” appears to be a typographical error and applicant intended to use the term -- another--.
Claim 1 line 22 “antoher” appears to be a typographical error and applicant intended to use the term -- another--.
Claim 1 line 25 “switchs” appears to be a typographical error and applicant intended to use the term -- switches--.
Claim 1 line 36 “switchs arraies” appears to be a typographical error and applicant intended to use the term – switches arrays--.
Claim 1 line 46 “switchs” appears to be a typographical error and applicant intended to use the term – switches--.
Appropriate correction is required.
Claim 11 is objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim should refer to other claims in the alternative only. See MPEP § 608.01(n). Accordingly, the claim has not been further treated on the merits.
Claims 12-17 are objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim cannot depend from any other multiple dependent claim. See MPEP § 608.01(n). Accordingly, the claims 12-17 have not been further treated on the merits.
The claims are objected to because they include reference characters which are not enclosed within parentheses.
Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 contains limitations directed to both the apparatus lines (1-32) and the method of using the apparatus (lines 32-52). Per MPEP 2173.05(p)(II) “A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b)”.
Claims 2 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “the same end and the reverse end" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the same end and the reverse end" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claims 3 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3 and 13 contain the limitation “the fractional frequency is of a oscillator” and it is unclear to the examiner whether the fractional frequency is generated by an oscillator or the fractional frequency is a similar frequency to the frequency generated by an oscillator.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hu et al. (US 2023/0046326) discloses a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.
Lin et al. (US 2022/0149849) discloses a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
Okada (US 2016/0226656) discloses a phase detector includes an amplifier and an analog-to-digital converter. The amplifier amplifies a voltage of a signal which is output from a digitally-controlled oscillator and is held based on a reference signal. The analog-to-digital converter converts the voltage amplified by the amplifier into a digital signal, based on the reference signal.
Galton et al. (US 2010/0039182) discloses a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage. In contrast, the differential integrator operates on the differential-mode voltage from the two loop filter halves but attenuates their common-mode voltage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2896