DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 05/28/2026, for application number 18/954,607 has been received and entered into record. Claims 1, 3, 4, 5, 8-10, 15, and 17-19 are amended. Claims 5, 7, 14, 16 and 20 are cancelled. Thus, claims 1-4, 6, 8-13, 15 and 17-19 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 8-11, 13, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0225732 A1) in view of Reddy et al. (US 2022/0011842 A1).
Regarding claim 1, He teaches an information handling system (Figure 1A, IHS 100) comprising:
a memory (“BIOS 124 may include non-volatile memory, such as NVRAM,” par 0024 and Figure 1A) to store a user selectable thermal table (“The user-selectable power setting in the BIOS, such as shown in the example of FIG. 2, may be correlated with particular settings and values for the information handling system through a user-selectable power table (USPT).” Par 0034 and Figures 6 and 7); and
set a power level of the information handling system to a lower power mode (“A line 804 shows that at the “Balanced” profile, the CPU is restricted to a lower power setting… A line 806 shows that at the “Power Saver” profile, the CPU is further restricted to an even lower power setting” par 0087 and “The list of items may include options such as “High Performance,” “Balanced,” and “Power Saver,” each of which corresponds to a certain sustained power setting and/or other settings that can be obtained from a lookup table.” Par 0030) [the lookup table defines a hierarchy of power profiles that allows the system to set a power level to the next lower power mode to address system shortcomings], wherein the lower power mode is a next lower power mode as compared to a current power state of the information handling system (Figures 6-8, each lower power level has lower CPU power than the previous higher power level, see Figure 8), wherein the lower power mode is based on the user selectable thermal table (“Tables, such as … FIG. 6 and FIG. 7, may be used to perform mapping of the received user input in the BIOS, which may be a user-friendly descriptive text, to the sustained power setting and/or other power or thermal settings. The mapped values are then transmitted to the appropriate components, such as by transmitting a corresponding PL1 value to the CPU” par 0036 and “wherein the user input specifying the power setting comprises a value corresponding to a selected entry in a user-selectable power table (USPT),” claim 7).
However, He does not explicitly teach an embedded controller to communicate with the memory, the embedded controller to: while the embedded controller is in a high power state and a basic input/output system (BIOS) and an operating system (OS) of the information handling system are in a sleep state, perform operations to enter the information handling system into a modern standby; determine a failure of the information handling system to enter the modern standby, wherein the embedded controller remains in the high power state based on the failure of the information handling system to enter the modern standby; based on the failure, the embedded controller to: wake up both a basic input/output system (BIOS) and an operating system (OS) of the information handling system; after the information handling system is set to the lower power mode, determine whether a retry count is greater than a threshold; in response to the retry count being greater than the threshold, force the information handling system into a hibernation mode; and in response to the retry count being less than the threshold, repeat the operations to enter the information handling system into the modern standby.
In the analogous art, Reddy teaches an embedded controller to communicate with the memory (“controller 112 may include a processor 128 and memory 130.” Par 0026 and Figure 1), the embedded controller to:
while the embedded controller is in a high power state and a basic input/output system (BIOS) and an operating system (OS) of the information handling system are in a sleep state, perform operations to enter the information handling system into a modern standby (“In Modern Standby, no OS software activity runs.” Par 0020 and “the notification message [to the embedded controller] includes an instruction to the embedded controller to perform a first process for placing first hardware components in the first operating mode and to start a timer for completing the first process… a first operating mode, e.g., Modern Standby.” Par 0009 and paragraph 11) [the EC remains active while OS and BIOS are in low power sleep states];
determine a failure of the information handling system to enter the modern standby (“a second circuitry to detect, after expiration of the time-out period, a failure of the first process; [to place device in modern standby]” par 0123), wherein the embedded controller remains in the high power state based on the failure of the information handling system to enter the modern standby (“At 226, controller 112 waits until the time-out period has expired. At the expiration of time-out period, controller 112 determines if either software or hardware did not enter the low power state, e.g., either SW or HW DRIPs was not achieved… controller 112 sends a message to OS 106 notifying it that software or hardware or both did not enter the low power state. ” Par 0032 and paragraph 12) [the EC uses a timer to determine failure to enter modern standby and remains active];
based on the failure, the embedded controller to:
wake up both a basic input/output system (BIOS) and an operating system (OS) of the information handling system (“A hardware interrupt (e.g., wake event 228) causes the system to exit Modern Standby…In Modern Standby, no OS software activity runs” par 0020 and “The OS may determine an operation to remove the cause, i.e., fix the problem, and perform the operation one or more times.” Par 0012 and “BIOS 104 is firmware which runs on the Processor 102.” Par 0023 and paragraph 32 and Figure 1) [the EC’S failure notification corresponds to a wake up event that triggers the processor to exit its suspended state, waking up the OS and the BIOS];
after the information handling system is set to the lower power mode, determine whether a retry count is greater than a threshold (“The controller 112 also initializes a counter for counting a number of fix attempts.” Par 0032 and “determine if the count exceeds a maximum number of attempts to fix the cause of the failure.” Par 0129);
in response to the retry count being greater than the threshold, force the information handling system into a hibernation mode (“If the cause of the failure is not fixed after the maximum number of attempts, the power managing device sends a message to operating system 452 instructing it to place the computing device 400 in a second operating mode, e.g., hibernate (S4).” Par 0093); and
in response to the retry count being less than the threshold, repeat the operations to enter the information handling system into the modern standby (“If the operation did not cure the problem, a second attempt to cure the problem may be performed, i.e., the operation may be repeated…Additional attempts may be made to cure the problem provided the number of additional attempts is less than a predetermined number,” par 0033).
It would have been obvious to a person having ordinary skill in the art, having the teachings of He and Reddy before him before the effective filing date of the claimed invention, to have modified He to incorporate the teachings of Reddy to include a threshold for retrying to enter modern standby because both are directed at system power control based on failures and shortcomings. Setting a threshold number of retry attempts to enter modern standby and forcing the system to hibernate once the threshold is exceeded to lower power consumption. (Reddy, paragraph 35)
Claim 10 corresponds to claim 1 and is rejected accordingly.
Regarding claim 2, He and Reddy teach the information handling system of claim 1. Reddy further teaches wherein the process further to:
determine whether the operation to enter the information handling system into the modern standby has been repeated a predetermined amount of time (“ in the case of hardware not entering the low power state, controller 112 determines that the cause for the failure of the first process is related to particular hardware devices or components. The controller 112 also initializes a counter for counting a number of fix attempts.” Par 0032 and “determine if the count exceeds a maximum number of attempts to fix the cause of the failure.” Par 0129); and
in response to the operations being repeated the predetermined amount of time, trigger the information handling system to enter into a hibernation state (“If the cause of the failure is not fixed after the maximum number of attempts, the power managing device sends a message to operating system 452 instructing it to place the computing device 400 in a second operating mode, e.g., hibernate (S4).” Par 0093).
Claim 11 corresponds to claim 2 and is rejected accordingly.
Regarding claim 4, He and Reddy teach the information handling system of claim 1. He further teaches wherein the embedded controller to: lower the power level in a linear manner (“The setting 204 may alternatively be, as another example, a slider bar for selecting between a plurality of profiles for power management.” Par 0030 and “The BIOS may set the PL1 value through the MSR bus and/or by transmitting a command to the EC to set the PL1 value through the PECI bus.” Par 0033 and Figures 6 and 7) [the user can select power profiles through a linear slider bar which the BIOS then instructs EC to set the specific, progressively lower power limits for the processor; choosing the next lower power mode corresponds to changing the power level in a linear manner].
Claim 13 corresponds to claim 4 and is rejected accordingly.
Regarding claim 8, He and Reddy teach the information handling system of claim 1. Reddy further teaches wherein the embedded controller remains in the high power state based on a power management capability not operating during the operations to enter the information handling system into the modern standby (“In Modern Standby, no OS software activity runs.” Par 0020 and “the notification message [to the embedded controller] includes an instruction to the embedded controller to perform a first process for placing first hardware components in the first operating mode and to start a timer for completing the first process … a first operating mode, e.g., Modern Standby.” Par 0009 and paragraph 11) [when the system’s capability to achieve a low power state fails to transition (residency is not achieved) the EC remains active].
Claim 17 corresponds to claim 8 and is rejected accordingly.
Regarding claim 9, He and Reddy teach the information handling system of claim 1. He further teaches wherein the embedded controller is an embedded controller of the information handling system (Figure 1A, controller 128 and paragraph 29).
Claim 18 corresponds to claim 9 and is rejected accordingly.
Claims 3, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over He and Reddy in view of Grobelny et al. (US 2019/0258309 A1).
Regarding claim 3, He and Reddy teaches the information handling system of claim 1. However, He and Reddy do not explicitly teach wherein based on the failure, the embedded controller to: record the failure in the memory.
In the analogous art, Grobelny teaches wherein based on the failure, the embedded controller to: record the failure in the memory (“EC 190 may log information that indicates that the status signal has not been received. In one or more embodiments, EC 190 logging the information that indicates that the status signal has not been received may include providing EC event 352 to IHSFW 172. For example, IHSFW 172 may provide log event 362 to log 370. In one instance, log 370 may include a memory medium that stores the information that indicates that the status signal has not been received… logging the information that indicates that the status signal has not been received from device 330 may include flagging device 330 as a failing participant.” Par 0055 and paragraph 53, 56, 57 and Figures 1, 3A-C, 5, steps 525, 530) [after a signal was sent to enter a low power state, the system will determine if the status was received; if the signal was not received, the system will determine failure and log information in the memory].
It would have been obvious to a person having ordinary skill in the art, having the teachings of He, Reddy and Grobelny before him before the effective filing date of the claimed invention, to have modified He and Reddy to incorporate the teachings of Grobelny to record the failure in memory to allow for future system diagnostics to allow the system to recover and provide data for future troubleshooting. Flagging a failing participant can allow for side-band monitoring and power management policies to reduce power consumptions of these participants. (Grobelny, paragraph 19)
Claim 12 corresponds to claim 3 and is rejected accordingly.
Claim 19 corresponds to claims 1, 2, and 3 combined and is rejected accordingly.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over He and Reddy in view of Chaiken et al. (US 2022/0269574 A1).
Regarding claim 6, He and Reddy teach the information handling system of claim 1. However, He and Reddy do not explicitly teach wherein based on the failure, the embedded controller further to: set a thermal level of the information handling system to a lower thermal stage.
In the analogous art, Chaiken teaches wherein based on the failure, the embedded controller further to: set a thermal level of the information handling system to a lower thermal stage (“In addition to or in lieu of the actions described above for mitigating failure to enter Modern Standby, management controller 112 may take or cause one or more other mitigating actions … caused by expiration of a respective timer. Such one or more other mitigating actions may include … changes in rotational velocity of an air mover (e.g., fan or blower) of information handling system 102,” par 0051) [the velocity of an air mover may correspond to thermal level of the IHS; in one embodiment, changing the velocity of an air mover to a lower speed lowers the thermal stage of the IHS].
It would have been obvious to a person having ordinary skill in the art, having the teachings of He, Reddy and Chaiken before him before the effective filing date of the claimed invention, to have modified He and Reddy to incorporate the teachings of Chaiken to set a lower thermal stage in response to failing to enter modern standby to prevent overheating and battery depletion. (Chaiken, paragraph 47)
Claim 15 corresponds to claim 6 and is rejected accordingly.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Kosugi et al. (US 2019/0073023 A1) teaches an information processing device that suppresses the device from entering a state unintended by a user in a standby mode. It further teaches a multi stage transition into lower power consumption states based on the modern standby mode transition.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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