DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-9 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gunnam et al. (US 2018/0189155) in view of Muchherla et al. (US 11,188,459).
With respect to claim 1, Gunnam et al. teaches a memory array (see Fig. 2 and paragraphs 23 and 41; storage class memory device 110 may operate as a cache between the primary memory 130 and the secondary memory 120… storage class memory device 110 includes a storage class memory array 220); and
control logic, operatively coupled to the memory array (see Fig. 2A and paragraph 41; controller 210 coupled to array 220), to perform operations comprising:
causing a first write operation to be performed to write host data to a first cache block of the memory array (see paragraph 57; the controller 210 may receive an access command to write DATA_1 to page 221A (e.g., may receive a write command));
detecting, during the first write operation, a block address change reflecting block switching to write the host data to a second cache block of the memory array (see paragraph 57; controller 210 may remap the logical address (indicated in the write command) to the physical address of another page in the storage class memory array 220 when there is a failure while writing DATA_1 to page 221A).
Gunnam et al. does not teach after detecting the block address change, determining whether the first write operation is complete; and in response to determining that the first write operation is complete, initiating a second write operation to write the host data to the second cache block.
However, Muchherla et al. teaches the processing device writes a first portion of the host data to a first available data block of the memory sub-system, where the first available data block is associated with a first write mode… the processing device receives an indication that a second available data block of the memory sub-system is available for host data (i.e., block address change indication), where the second available data block is associated with a second write mode; and the processing device, in response to determining to write the second portion of the host data to the second available data block, writes the second portion of the host data to the second available data block in the second write mode (i.e., after first portion of data is finished being written in first block, the second portion of data is written in second block) (see column 8, lines 39-67 and column 9, lines 1-38).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Gunnam et al. to include the above mentioned to improve performance of the memory sub-system as the overall write operation latency can be reduced (see Muchherla, column 4, lines 15-17).
With respect to claim 2, Gunnam et al. teaches wherein detecting the block address change comprises receiving, from a memory sub-system controller, information indicative of the block address change (see paragraph 57; remap information).
With respect to claim 7, Gunnam et al. does not teach wherein the first cache block stores data having a first access type, and wherein the second cache block stores data having a second access type different from the first access type.
However, Muchherla et al. teaches wherein the first cache block stores data having a first access type (see column 8, lines 39-42; processing device writes a first portion of the host data to a first available data block of the memory sub-system, where the first available data block is associated with a first write mode), and wherein the second cache block stores data having a second access type different from the first access type (see column 8, lines 58-61; the processing device receives an indication that a second available data block of the memory sub-system is available for host data, where the second available data block is associated with a second write mode).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Gunnam et al. to include the above mentioned to improve performance of the memory sub-system as the overall write operation latency can be reduced (see Muchherla, column 4, lines 15-17).
With respect to claim 8, Gunnam et al. teaches causing, by a processing device, a first write operation to be performed to write host data to a first cache block of a memory array of a memory device (see paragraph 57; the controller 210 may receive an access command to write DATA_1 to page 221A (e.g., may receive a write command));
detecting, by the processing device during the first write operation, a block address change reflecting block switching to write the host data to a second cache block of the memory array (see paragraph 57; controller 210 may remap the logical address (indicated in the write command) to the physical address of another page in the storage class memory array 220 when there is a failure while writing DATA_1 to page 221A).
Gunnam et al. does not teach after detecting the block address change, determining, by the processing device, whether the first write operation is complete; and in response to determining that the first write operation is complete, initiating, by the processing device, a second write operation to write the host data to the second cache block.
However, Muchherla et al. teaches the processing device writes a first portion of the host data to a first available data block of the memory sub-system, where the first available data block is associated with a first write mode… the processing device receives an indication that a second available data block of the memory sub-system is available for host data (i.e., block address change indication), where the second available data block is associated with a second write mode; and the processing device, in response to determining to write the second portion of the host data to the second available data block, writes the second portion of the host data to the second available data block in the second write mode (i.e., after first portion of data is finished being written in first block, the second portion of data is written in second block) (see column 8, lines 39-67 and column 9, lines 1-38).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gunnam et al. to include the above mentioned to improve performance of the memory sub-system as the overall write operation latency can be reduced (see Muchherla, column 4, lines 15-17).
With respect to claim 9, Gunnam et al. teaches wherein detecting the block address change comprises receiving, from a memory sub-system controller, information indicative of the block address change (see paragraph 57; remap information).
With respect to claim 14, Gunnam et al. does not teach wherein the first cache block stores data having a first access type, and wherein the second cache block stores data having a second access type different from the first access type.
However, Muchherla et al. teaches wherein the first cache block stores data having a first access type (see column 8, lines 39-42; processing device writes a first portion of the host data to a first available data block of the memory sub-system, where the first available data block is associated with a first write mode), and wherein the second cache block stores data having a second access type different from the first access type (see column 8, lines 58-61; the processing device receives an indication that a second available data block of the memory sub-system is available for host data, where the second available data block is associated with a second write mode).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gunnam et al. to include the above mentioned to improve performance of the memory sub-system as the overall write operation latency can be reduced (see Muchherla, column 4, lines 15-17).
With respect to claim 15, Gunnam et al. teaches causing a first write operation to be performed to write host data to a first cache block of a memory array of a memory device (see paragraph 57; the controller 210 may receive an access command to write DATA_1 to page 221A (e.g., may receive a write command));
detecting, during the first write operation, a block address change reflecting block switching to write the host data to a second cache block of the memory array (see paragraph 57; controller 210 may remap the logical address (indicated in the write command) to the physical address of another page in the storage class memory array 220 when there is a failure while writing DATA_1 to page 221A).
Gunnam et al. does not teach after detecting the block address change, determining whether the first write operation is complete; and in response to determining that the first write operation is complete, initiating a second write operation to write the host data to the second cache block.
However, Muchherla et al. teaches the processing device writes a first portion of the host data to a first available data block of the memory sub-system, where the first available data block is associated with a first write mode… the processing device receives an indication that a second available data block of the memory sub-system is available for host data (i.e., block address change indication), where the second available data block is associated with a second write mode; and the processing device, in response to determining to write the second portion of the host data to the second available data block, writes the second portion of the host data to the second available data block in the second write mode (i.e., after first portion of data is finished being written in first block, the second portion of data is written in second block) (see column 8, lines 39-67 and column 9, lines 1-38).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gunnam et al. to include the above mentioned to improve performance of the memory sub-system as the overall write operation latency can be reduced (see Muchherla, column 4, lines 15-17).
With respect to claim 16, Gunnam et al. teaches wherein detecting the block address change comprises receiving, from a memory sub-system controller, information indicative of the block address change (see paragraph 57; remap information).
Claim(s) 3, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gunnam et al. (US 2018/0189155) and Muchherla et al. (US 11,188,459) as applied to claims 1-2 above, and further in view of Lu et al. (US 11,977,752).
With respect to claim 3, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change from the memory sub-system controller comprises receiving a Set Feature command.
However, Lu et al. teaches wherein the address control circuit 1112 may automatically change the first address information as a third address information, which indicates a third data unit at a third plane different from the first plane, in response to a bit map information or a set-feature signal sent from the flash memory controller (see column 21, lines 59-67)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the whole performance of a storage device (see Lu, column 41, lines 55-61).
With respect to claim 10, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change from the memory sub-system controller comprises receiving a Set Feature command.
However, Lu et al. teaches wherein the address control circuit 1112 may automatically change the first address information as a third address information, which indicates a third data unit at a third plane different from the first plane, in response to a bit map information or a set-feature signal sent from the flash memory controller (see column 21, lines 59-67)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the whole performance of a storage device (see Lu, column 41, lines 55-61).
With respect to claim 17, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change from the memory sub-system controller comprises receiving a Set Feature command.
However, Lu et al. teaches wherein the address control circuit 1112 may automatically change the first address information as a third address information, which indicates a third data unit at a third plane different from the first plane, in response to a bit map information or a set-feature signal sent from the flash memory controller (see column 21, lines 59-67)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the whole performance of a storage device (see Lu, column 41, lines 55-61).
Claim(s) 4, 11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gunnam et al. (US 2018/0189155) and Muchherla et al. (US 11,188,459) as applied to claims 1-2 above, and further in view of Hoya (US 12,217,781).
With respect to claim 4, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change comprises receiving a prefix command.
However, Hoya teaches wherein the controller 2 may supply a prefix command CMDx to the memory device 1… By receiving the prefix command CMDx, the memory device 1 can recognize that a write-back address ADR2 is to be transmitted after the read address ADR1 and the read command CMD1 (see column 19, lines 45-54).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the operating characteristics of memory devices (see Hoya, column 11, lines 51-53 and column 22, lines 31-33).
With respect to claim 11, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change comprises receiving a prefix command.
However, Hoya teaches wherein the controller 2 may supply a prefix command CMDx to the memory device 1… By receiving the prefix command CMDx, the memory device 1 can recognize that a write-back address ADR2 is to be transmitted after the read address ADR1 and the read command CMD1 (see column 19, lines 45-54).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the operating characteristics of memory devices (see Hoya, column 11, lines 51-53 and column 22, lines 31-33).
With respect to claim 18, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change comprises receiving a prefix command.
However, Hoya teaches wherein the controller 2 may supply a prefix command CMDx to the memory device 1… By receiving the prefix command CMDx, the memory device 1 can recognize that a write-back address ADR2 is to be transmitted after the read address ADR1 and the read command CMD1 (see column 19, lines 45-54).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the operating characteristics of memory devices (see Hoya, column 11, lines 51-53 and column 22, lines 31-33).
Claim(s) 5, 12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gunnam et al. (US 2018/0189155) and Muchherla et al. (US 11,188,459) as applied to claims 1-2 above, and further in view of Siciliani et al. (US 9,881,675).
With respect to claim 5, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change comprises receiving address cycle information.
However, Siciliani et al. teaches wherein a memory controller can use a defined number of address cycles to address the individual memory units in the NAND memory (e.g., five address cycles in a legacy mode or six address cycles) ... In one configuration, the NAND memory can be capable of switching from five address cycles to six address cycles (see column 4, lines 46-61 and column 9, lines 4-13).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the whole performance of a storage device (see Siciliani, column 4, lines 12-20).
With respect to claim 12, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change comprises receiving address cycle information.
However, Siciliani et al. teaches wherein a memory controller can use a defined number of address cycles to address the individual memory units in the NAND memory (e.g., five address cycles in a legacy mode or six address cycles) ... In one configuration, the NAND memory can be capable of switching from five address cycles to six address cycles (see column 4, lines 46-61 and column 9, lines 4-13).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the whole performance of a storage device (see Siciliani, column 4, lines 12-20).
With respect to claim 19, Gunnam et al. and Muchherla et al. do not teach wherein receiving the information indicative of the block address change comprises receiving address cycle information.
However, Siciliani et al. teaches wherein a memory controller can use a defined number of address cycles to address the individual memory units in the NAND memory (e.g., five address cycles in a legacy mode or six address cycles) ... In one configuration, the NAND memory can be capable of switching from five address cycles to six address cycles (see column 4, lines 46-61 and column 9, lines 4-13).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gunnam et al. and Muchherla et al. to include the above mentioned to improve the whole performance of a storage device (see Siciliani, column 4, lines 12-20).
Claim(s) 6, 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gunnam et al. (US 2018/0189155) and Muchherla et al. (US 11,188,459) as applied to claims 1-2 above, and further in view of Ning et al. (US 11,899,971).
With respect to claim 6, Gunnam et al. and Muchherla et al. do not teach wherein detecting the block address change comprises performing a block address comparison.
However, Ning et al. teaches wherein the address information pointed to by the write command is compared with the address information stored in the preset memory space… If the address information pointed to by the write command is identical to the address information stored in the preset memory space 30, this means that the address information pointed to by the write command is stored in the memory bit ADD of the preset memory space 30. In this case, it is stopped performing the write operation on the memory cell corresponding to the address information pointed to by the write command, and the write operation is performed on a spare memory cell (see column 9, lines 27-50).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Gunnam et al. and Muchherla et al. to include the above mentioned to greatly improve the reliability of the memory device and prolong the lifespan of the memory device (see Ning, column 1, lines 34-37).
With respect to claim 13, Gunnam et al. and Muchherla et al. do not teach wherein detecting the block address change comprises performing a block address comparison.
However, Ning et al. teaches wherein the address information pointed to by the write command is compared with the address information stored in the preset memory space… If the address information pointed to by the write command is identical to the address information stored in the preset memory space 30, this means that the address information pointed to by the write command is stored in the memory bit ADD of the preset memory space 30. In this case, it is stopped performing the write operation on the memory cell corresponding to the address information pointed to by the write command, and the write operation is performed on a spare memory cell (see column 9, lines 27-50).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Gunnam et al. and Muchherla et al. to include the above mentioned to greatly improve the reliability of the memory device and prolong the lifespan of the memory device (see Ning, column 1, lines 34-37).
With respect to claim 20, Gunnam et al. and Muchherla et al. do not teach wherein detecting the block address change comprises performing a block address comparison.
However, Ning et al. teaches wherein the address information pointed to by the write command is compared with the address information stored in the preset memory space… If the address information pointed to by the write command is identical to the address information stored in the preset memory space 30, this means that the address information pointed to by the write command is stored in the memory bit ADD of the preset memory space 30. In this case, it is stopped performing the write operation on the memory cell corresponding to the address information pointed to by the write command, and the write operation is performed on a spare memory cell (see column 9, lines 27-50).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Gunnam et al. and Muchherla et al. to include the above mentioned to greatly improve the reliability of the memory device and prolong the lifespan of the memory device (see Ning, column 1, lines 34-37).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yan et al. (US2011/0032774) teaches a process for implementing a memory block switching technique during a write operation (see paragraph 58).
Sandberg et al. (US 10,712,965) teaches transferring data between address ranges in memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139