Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 10- 2023-0168632, filed on 11/08/2023.
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 11/21/2024 & 04/29/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Election/Restrictions
Applicant’s arguments filed on 04/22/2026 in response to the restriction requirement set forth in the Office Action mailed February 25, 2026 have been fully considered but are not persuasive.
The restriction requirement is therefore maintained.
Applicant contends that simultaneous examination of the identified inventions would not present an undue burden because the inventions are classified in the same class and are directed to similar subject matter.
However, this argument is not persuasive.
The inventions as identified in the restriction requirement are directed to independent and distinct inventions, and examination of each invention would require a separate search and examination, thereby imposing an undue burden on the office. Classification alone does not determine whether a restriction requirement is proper, as the determination is based on whether the inventions are independent or distinct.
Applicant’s reliance on MPEP 803 is also not persuasive. The present restriction requirement is based on independent and distinct inventions, and not merely on a plurality of species.
Accordingly, the restriction requirement is maintained, and Applicant’s traversal is not persuasive.
Applicant’s election of Group I (i.e., claims 1-20) in the reply filed on 04/22/2026 is acknowledged. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WANG et al. (Pub. No.: US 2022/0214907).
Regarding independent claims 1 and 20, WANG discloses a memory device, comprising:
a memory module (Fig.1: Hardware) comprising a normal memory area (Fig.3: physical memory 202) and a swap memory area (Fig.3: swap space 203),
wherein the swap memory area (Fig.3: swap space 203) is configured to store swapped-out data (Fig.3 and [0102]: When a ratio of available memory pages remaining in physical memory to total memory pages in the physical memory reaches a water level specified for the physical memory (that is, when physical memory usage is tight, or the physical memory is insufficient), memory swapping is performed for the swappable memory, to be specific, part or all of the data in the swappable memory is stored into swap space in a nonvolatile memory); and
a memory processing unit (Fig.3: Processor 201) configured to provide a host with physical address information corresponding to an additional memory area (Fig.3: swappable memory shown in 202) determined based on a size of the swapped-out data and the normal memory area (Fig.3: physical memory 202) (Fig.3 & Fig.4 and [0090]: when memory swapping needs to be performed between the physical memory in the volatile memory 202 and the swap space in the nonvolatile memory, the processor 201 performs page swapping on a selected memory page between the physical memory and the swap space. Specifically, the processor (e.g., CPU) 201 may perform a virtual machine memory management method shown in FIG. 4, including but not limited to the following operations).
Regarding claim 2, WANG teaches wherein the physical address information is a physical address corresponding to a range increased from a default size of the memory module by a difference between an original size of the swapped-out data and a size of the swap memory area (Fig.3, [0076] and [0134]: freeing memory via swapping increases available memory capacity for allocation, thereby effectively increasing an addressable memory range based on swapped-out data).
Regarding claim 3, WANG teaches wherein an address of the additional memory corresponds to the swap memory area of the memory module, and a size of the additional memory area is greater than a size of the swap memory area (Fig.3, [0068] and [0134]: data is moved to swap space while freed physical memory is reused, resulting in an effective usable memory space exceeding the swap storage region).
Regarding claim 4, WANG teaches wherein the memory module is configured to store page data allocated to execute an application program in an operating system (Fig.3 and [0063]-[0065]: memory stores code and data of virtual machine applications executed in an operating system).
Regarding claim 5, WANG teaches wherein the memory processing unit is configured to detect cold data from data stored in the memory module based on at least one of an access count or an access time of data recorded in the normal memory area (Fig.3 and [0075]-[0077]: selecting memory pages for swapping based on memory usage characteristics, which inherently corresponds to identifying cold data).
Regarding claim 15, WANG teaches wherein a size of the additional memory area varies depending on a compression rate of the swapped-out data (Fig.3 and [0076]: Memory swapping means that when a ratio of available memory pages remaining in physical memory to total memory pages in the physical memory reaches a threshold specified for the physical memory, data on some memory pages in the physical memory may be stored into a magnetic disk, to free up memory space for anew application requirement. When the data on the memory pages needs to be used, the data is then transferred back to the physical memory).
Regarding claim 16, WANG teaches wherein the memory processing unit is further configured to: transmit the swapped-out data to an external device comprising at least one of a memory or a storage, and manage mapping information between a physical address of the swapped-out data and a physical address provided to a host side (Fig.3, [0068] and [0127]: The nonvolatile memory may be configured to provide swap space. The swap space is a segment of storage space (or referred to as address space) in the nonvolatile memory. The swap space is used to store data swapped from the physical memory. In other words, when available memory in the physical memory is insufficient, part of data stored in the physical memory, for example, data on memory pages, data in blocks, or data in storage units at a granularity of another type, may be stored into the swap space in the nonvolatile memory).
Regarding claim 17, WANG teaches wherein the memory processing unit is further configured to periodically perform detection and swap-out operations on cold data without a swap-out request by the host (Fig.3, [0068] and [0127]: The nonvolatile memory may be configured to provide swap space. The swap space is a segment of storage space (or referred to as address space) in the nonvolatile memory. The swap space is used to store data swapped from the physical memory. In other words, when available memory in the physical memory is insufficient, part of data stored in the physical memory, for example, data on memory pages, data in blocks, or data in storage units at a granularity of another type, may be stored into the swap space in the nonvolatile memory).
Regarding claim 18, WANG teaches wherein when a size of the normal memory area is insufficient, the memory device performs a swap-out operation without a request by the host (Fig.3, [0068] and [0127]: The nonvolatile memory may be configured to provide swap space. The swap space is a segment of storage space (or referred to as address space) in the nonvolatile memory. The swap space is used to store data swapped from the physical memory. In other words, when available memory in the physical memory is insufficient, part of data stored in the physical memory, for example, data on memory pages, data in blocks, or data in storage units at a granularity of another type, may be stored into the swap space in the nonvolatile memory).
Regarding claim 19, WANG teaches wherein the swap-out operation comprises compressing the swapped-out data in the normal memory area, and storing the compressed swapped-out data in the swap memory area (Fig.3, [0068] and [0127]: The nonvolatile memory may be configured to provide swap space. The swap space is a segment of storage space (or referred to as address space) in the nonvolatile memory. The swap space is used to store data swapped from the physical memory. In other words, when available memory in the physical memory is insufficient, part of data stored in the physical memory, for example, data on memory pages, data in blocks, or data in storage units at a granularity of another type, may be stored into the swap space in the nonvolatile memory).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-14 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al. (Pub. No.: US 2022/0214907) in view of Agarwal et al. (Pub. No.: US 2015/0039835).
Regarding claim 6, WANG does not specifically teach wherein the memory processing unit is further configured to determine data having at least one of an access count that is lower than access counts of other pieces of data recorded in the normal memory area, or an access time preceding access times of other pieces of data in the normal memory area, to be the cold data.
However, Agarwal teaches wherein the memory processing unit is further configured to determine data having at least one of an access count that is lower than access counts of other pieces of data recorded in the normal memory area, or an access time preceding access times of other pieces of data in the normal memory area, to be the cold data (Fig.1A, [0013] and [0014]: Reference to any of the MFU, LRU, and hot spot detection algorithms generally defines a priority queue where "hot" data is stored in cache memory when a specified threshold of data transfer activity or heat quotient is achieved. In some embodiments, the threshold level of data transfer activity is satisfied upon receipt of at least three data transfer requests (or "I/O hits"). If no free data windows are available to receive the hot data, then data residing at a low priority tier is removed from cache memory. The data windows freed as a result of removing the cold data from cache memory are then used to cache the hot data).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a least recently used (LRU) algorithm, as taught by Agarwal into the virtual machine memory management method of WANG to improve the efficiency of data management and selection for removal or retention.
Regarding claim 7, Agarwal teaches wherein the memory processing unit is further configured to: in response to a memory access request received from the host, update an access count of a page corresponding to the memory access request, and process the memory access request after updating the access count (Fig.2 and [0014]: Reference to any of the MFU, LRU, and hot spot detection algorithms generally defines a priority queue where "hot" data is stored in cache memory when a specified threshold of data transfer activity or heat quotient is achieved. In some embodiments, the threshold level of data transfer activity is satisfied upon receipt of at least three data transfer requests (or "I/O hits"). If no free data windows are available to receive the hot data, then data residing at a low priority tier is removed from cache memory. The data windows freed as a result of removing the cold data from cache memory are then used to cache the hot data).
Regarding claim 8, Agarwal teaches wherein the memory processing unit is further configured to: swap out data of a first address determined to correspond to the cold data to a second address, and update mapping information in data access information by mapping the first address from a host side onto the second address (Fig.2, [0014] and [0028]: Agarwal discloses removing lower-priority (cold) data from cache memory to free space, which corresponds to moving data from one storage location to another and updating data location references, and it would have been obvious to implement such relocation using address mapping techniques).
Regarding claim 9, Agarwal teaches wherein the memory processing unit is further configured to, when receiving an access request to the first address from the host, provide the host with access to the second address (Fig.1A and [0018]).
Regarding claim 10, Agarwal teaches wherein the memory processing unit is further configured to: when a size of data of the second address is reduced, temporarily store data restored from reduced data in a buffer, and after transmitting the data temporarily stored in the buffer to the host, delete the data from the buffer (Fig.2 and [0028]).
Regarding claim 11, Agarwal teaches wherein the memory processing unit is further configured to: in response to an access count with respect to the data of the second address exceeding a threshold, store data restored from reduced data of the second address in a third address in the normal memory area, and provide the host with the restored data stored in the third address (Fig.1A and [0014]).
Regarding claim 12, Agarwal teaches wherein the first address is an address belonging to the normal memory area of a memory side, and the second address is an address belonging to the swap memory area of the memory side (Fig.1A, [0013] and [0014]).
Regarding claim 13, Agarwal teaches wherein the memory processing unit is further configured to update mapping information in data access information by mapping a third address of a host side onto the first address of the memory side (Fig.1A and [0018]).
Regarding claim 14, Agarwal teaches wherein the memory processing unit is further configured to, when receiving an access request to the third address from the host, provide the host with access to the first address (Fig.1A and [0018]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lim (Pub. No.: US 2012/0151127) “METHOD OF STORING DATA IN A STORING DEVICE INCLUDING A VOLATILE MEMORY DEVICE”
Considered for teachings related to storage devices. More particularly, example embodiments relate to methods of storing data in storage devices including volatile memory devices.
Does not disclose or suggest wherein the swap memory area is configured to store swapped-out data; and a memory processing unit configured to provide a host with physical address information corresponding to an additional memory area determined based on a size of the swapped-out data and the normal memory area.
DAI (Pub. No.: US 2024/0311305) “CXL MEMORY MODULE, MEMORY DATA SWAP METHOD AND COMPUTER SYSTEM”
Considered for teachings related to the field of storage, in particular to a CXL memory module, a memory data swap method and a computer system.
Does not disclose or suggest wherein the swap memory area is configured to store swapped-out data; and a memory processing unit configured to provide a host with physical address information corresponding to an additional memory area determined based on a size of the swapped-out data and the normal memory area.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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