DETAILED ACTION
This office action is responsive to communication filed on May 21, 2026.
Response to Arguments
Applicant's arguments filed May 21, 2026 have been fully considered but they are not persuasive.
Applicant asserts, with respect to claim 2, that the Action relies on Murai as teaching different manufacture scale technologies based on the presence of analog circuitry in one chip and digital circuitry on another chip.
The Examiner respectfully disagrees. Murai is not relied upon as teaching different manufacture scale technologies simply based on the presence of analog circuitry in one chip and digital circuitry on another chip, but rather for teaching different manufacture scale technologies based on the different respective technologies used to manufacture the analog circuitry on one chip and the digital circuitry on the other chip, as detailed in the rejection of claim 2.
Applicant argues, with respect to claim 2, that Murai does not teach or suggest configuring semiconductor chips corresponding to different layers of a stacked structure, particularly chips that cooperatively implement portions of a single analog-to-digital converter, as being respectively manufactured according to different manufacture scale technologies as recited.
The Examiner respectfully disagrees. Murai teaches configuring semiconductor chips corresponding to different layers of a stacked structure as being respectively manufactured according to different manufacture scale technologies. Murai clearly shows in figure 1, that the chips (140, 240) form different layers of a stacked structure. Paragraph 0048 of Murai details the different manufacture scale technologies used to manufacture the respective chips (140, 240, see claim 2 rationale).
As per Applicant’s argument that Murai does not teach chips that cooperatively implement portions of a single analog-to-digital converter, Murao et al. and not Murai is relied upon to teach chips that cooperatively implement portions of a single analog-to-digital converter in the rejection of claim 2. As such, whether Murai teaches chips that cooperatively implement portions of a single analog-to-digital converter is inconsequential. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant further argues that claim 2 requires that the specific semiconductor chips of the second layer and the third layer of the claimed stacked structure, on which respective analog and digital components of the analog-to-digital converter are disposed, are themselves configured according to different manufacture scale technologies. Murao does not disclose any manufacture scale distinction between its second and third layer chips, and Murai does not address such a layered configuration or suggest applying its chip-level process distinctions to the particular arrangement of distributed analog-to-digital converter components across stacked layers as in Murao.
The Examiner respectfully disagrees. As per Applicant’s argument that Murao does not disclose any manufacture scale distinction between its second and third layer chips, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Murai, not Murao et al. is relied upon in the rejection of claim 2 to teach the manufacture scale distinction between the two chips (see claim 2 rationale).
As per Applicant’s argument that Murai does not address such a layered configuration or suggest applying its chip-level process distinctions to the particular arrangement of distributed analog-to-digital converter components across stacked layers as in Murao, the Examiner respectfully disagrees. As discussed above, Murai clearly shows in figure 1, that the chips (140, 240) form different layers of a stacked structure. The chip-level process distinctions of Murai are applied respectively to stacked analog and digital chips (140, 240, paragraph 0048, figure 1). In Murao et al., the stacked analog and digital chips (chip B, chip C) form distributed analog-to-digital converters (see figure 11, claim 2 rationale). Therefore, the combination of Murao et al. and Murai teaches a layered configuration and suggests applying chip-level process distinctions to the particular arrangement of distributed analog-to-digital converter components across stacked layers.
Applicant argues, with respect to the double patenting rejection of claim 2, that Murao and Murai at least fail to disclose or suggest "the semiconductor chip of the second layer is configured according to a first manufacture scale technology that is different from a second manufacture scale technology of the semiconductor chip of the third layer," as recited in Applicant's claim 2.
However, Murao is not relied upon in the double patenting rejection. The Examiner upholds that the combination of claim 1 of US Patent No. 12,185,012 and Murai teaches all of the limitations of claim 2 for at least the reasons provided in the double patenting rejection of claim 2.
As such, the rejection is maintained by the Examiner
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed March 20, 2026 was received and has been considered by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Murao et al. (US 2018/0220093) in view of Murai (US 2019/0013419).
The Examiner’s response to Applicant’s arguments, as outlined above, is hereby incorporated into the rejection of claims 2-5 and 9 by reference.
Consider claim 2, Murao et al. teaches:
An imaging device (see figure 11) having a stacked chip structure in which at least three semiconductor chips including a semiconductor chip of a first layer, a semiconductor chip of a second layer, and a semiconductor chip of a third layer are stacked (A first chip (chip A), a second chip (chip B) and a third chip (chip C) are included as shown in figure 11, paragraph 0083. The first, second and third chips are “stacked” as detailed in claims 1 and 4 of Murao et al.), the imaging device comprising:
a pixel array (21) including pixels two-dimensionally arranged in a matrix disposed on the semiconductor chip of the first layer (The first chip (chip A) includes pixel circuits (3n) as shown in figure 11, paragraph 0055. The pixel circuits are arranged two-dimensionally as shown in figure 2, paragraph 0048.);
an analog-to-digital converter (analog-to-digital converter circuit, 24n, paragraph 0062) configured to convert an analog pixel signal (Vopx) read from at least one of the pixels (3n) through a signal line (see figure 15) into a digital pixel signal (see paragraphs 0059 and 0062), wherein
an analog component (comparator, COMP) of the analog-to-digital converter (24n) is disposed on one of the semiconductor chip of the second layer or the semiconductor chip of the third layer (i.e. disposed on chip B, see figure 11, paragraph 0083); and
a digital component (counter, 51) of the analog-to-digital converter (24n) is disposed on the other of the semiconductor chip of the second layer or the semiconductor chip of the third layer (i.e. disposed on chip C, see figure 11, paragraph 0083).
However, Murao et al. does not explicitly teach that the semiconductor chip of the second layer is configured according to a first manufacture scale technology that is different from a second manufacture scale technology of the semiconductor chip of the third layer.
Murai similarly teaches an imaging device (figure 1) comprising a second chip (image sensor, 140, paragraph 0028) having an analog component (“the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component”, paragraph 0048) and a third chip (image processing chip, 240, paragraph 0035) having a digital component (“the image processing chip 240 includes a digital circuit as a main component”, paragraph 0048).
However, Murai additionally teaches that the semiconductor chip of the second layer (140) is configured according to a first manufacture scale technology (“the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology” paragraph 0048) that is different from a second manufacture scale technology of the semiconductor chip of the third layer (“In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by Murao et al. be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 3, and as applied to claim 2 above, Murao et al. does not explicitly teach the first and second manufacture scale technologies.
Murai further teaches that the second manufacture scale technology of the semiconductor chip of the third layer is more miniaturized than the first manufacture scale technology of the semiconductor chip of the second layer (“In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured. On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by Murao et al. be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 4, and as applied to claim 2 above, Murao et al. does not explicitly teach the first and second manufacture scale technologies.
Murai further teaches that a first manufacture cost for the first manufacture scale technology is different from a second manufacture cost for the second manufacture scale technology (“On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by Murao et al. be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 5, and as applied to claim 4 above, Murao et al. does not explicitly teach the first and second manufacture scale technologies.
Murai further teaches that the first manufacture cost is lower than the second manufacture cost (“On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by Murao et al. be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 9, and as applied to claim 2 above, Murao et al. further teaches that the analog component (COMP) and the digital component (51) of the analog-to-digital converter (24n) are configured to cooperate to perform a conversion operation for a same pixel signal (pixel signal Vopx, see figure 11, paragraphs 0053, 0054 and 0059).
Murao et al. does not explicitly teach that the first manufacture scale technology and the second manufacture scale technology are respectively configured based on performance requirements of the respective analog component and digital component.
Murai further teaches that the first manufacture scale technology and the second manufacture scale technology are respectively configured based on performance requirements of the respective analog component and digital component (“The image sensor 140 and the image processing chip 240 can be manufactured by different processes, so it is possible to select an optimum process for the respective semiconductor chips. In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured. On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first manufacture scale technology and the second manufacture scale technology of the respective analog component and digital component taught by the combination of Murao et al. and Murai be based on performance requirements as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Murao et al. (US 2018/0220093) in view of Murai (US 2019/0013419), as applied to claim 2 above, and further in view of Kim et al. (US 2018/0181827).
Consider claim 6, and as applied to claim 2 above, the combination of Murao et al. and Murai does not explicitly teach a semiconductor chip of a fourth layer.
Kim et al. similarly teaches a camera (figure 1A) with a controller (1200) comprised of multiple processors (first processor, 1200a, second processor, 1200b, figure 1B), paragraphs 0041 and 0048.
However, Kim et al. additionally teaches that AI circuitry is disposed on a semiconductor chip of a fourth layer (The AI circuitry may be implemented on a dedicated hardware chip or as a portion of a general-purpose processor, paragraphs 0051, 0081, 0115, 0134 and 0192), and the semiconductor chip of the fourth layer is configured according to a third manufacture scale technology that is different from at least one of the first manufacture scale technology or the second manufacture scale technology (Because the first manufacture scale technology is different from the second manufacture scale technology (see claim 2 rationale), the third manufacture scale technology is necessarily different from at least one of the first manufacture scale technology or the second manufacture scale technology.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging device taught by the combination of Murao et al. and Murai comprise an AI circuit disposed on a fourth semiconductor chip as taught by Kim et al. for the benefit of enabling a region of interest to be estimated and thus user satisfaction with a captured image to be increased (Kim et al., paragraphs 0051 and 0003).
Consider claim 7, and as applied to claim 6 above, Kim et al. teaches that the semiconductor chip of the fourth layer manufactured according to the third manufacture technology includes an AI circuit that performs digital processing (see paragraphs 0051, 0081, 0115, 0134 and 0192).
Murai teaches that the manufacture scale technology of a chip containing digital circuitry is more miniaturized than the manufacture scale technology of a chip containing analog circuitry (“In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured. On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the third manufacture scale technology taught by the combination of Murao et al., Murai and Kim et al. be more miniaturized than the first manufacture scale technology as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 8, and as applied to claim 6 above, the combination of Murao et al. and Murai does not explicitly teach than an AI circuit is disposed on the fourth semiconductor chip.
Kim et al. teaches that an AI circuit is disposed on the fourth semiconductor chip (The AI circuitry may be implemented on a dedicated hardware chip or as a portion of a general-purpose processor, paragraphs 0051, 0081, 0115, 0134 and 0192).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging device taught by the combination of Murao et al. and Murai comprise an AI circuit disposed on the fourth semiconductor chip as taught by Kim et al. for the benefit of enabling a region of interest to be estimated and thus user satisfaction with a captured image to be increased (Kim et al., paragraphs 0051 and 0003).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-5 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,185,012 in view of Murai (US 2019/0013419).
Consider claim 2, claim 1 of US 12,185,012 teaches (in parentheses): An imaging device having a stacked chip structure in which at least three semiconductor chips including a semiconductor chip of a first layer, a semiconductor chip of a second layer, and a semiconductor chip of a third layer are stacked, the imaging device comprising: (“An imaging device having a stacked chip structure including a first semiconductor chip of a first layer, a second semiconductor chip of a second layer, a third semiconductor chip of a third layer, and a fourth semiconductor chip of a fourth layer, the imaging device comprising:”)
a pixel array including pixels two-dimensionally arranged in a matrix disposed on the semiconductor chip of the first layer (“a pixel array including pixels two-dimensionally arranged in a matrix on the first semiconductor chip”);
an analog-to-digital converter configured to convert an analog pixel signal read from at least one of the pixels through a signal line into a digital pixel signal, wherein an analog component of the analog-to-digital converter is disposed on one of the semiconductor chip of the second layer or the semiconductor chip of the third layer; and a digital component of the analog-to-digital converter is disposed on the other of the semiconductor chip of the second layer or the semiconductor chip of the third layer (“an analog-digital conversion unit including an analog circuit and a digital circuit, the analog circuit being configured to convert an analog pixel signal read from respective pixels of the pixel array through a signal line into a digital pixel signal, the digital circuit being configured to receive the digital pixel signal from the analog circuit, wherein the analog circuit is disposed on the second semiconductor chip, the digital circuit is disposed on the third semiconductor chip”).
Claim 1 of US 12,185,012 does not explicitly teach that the semiconductor chip of the second layer is configured according to a first manufacture scale technology that is different from a second manufacture scale technology of the semiconductor chip of the third layer.
Murai similarly teaches an imaging device (figure 1) comprising a second chip (image sensor, 140, paragraph 0028) having an analog component (“the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component”, paragraph 0048) and a third chip (image processing chip, 240, paragraph 0035) having a digital component (“the image processing chip 240 includes a digital circuit as a main component”, paragraph 0048).
However, Murai additionally teaches that the semiconductor chip of the second layer (140) is configured according to a first manufacture scale technology (“the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology” paragraph 0048) that is different from a second manufacture scale technology of the semiconductor chip of the third layer (“In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by claim 1 of US 12,185,012 be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 3, and as applied to claim 2 above, claim 1 of US 12,185,012 does not explicitly teach the first and second manufacture scale technologies.
Murai further teaches that the second manufacture scale technology of the semiconductor chip of the third layer is more miniaturized than the first manufacture scale technology of the semiconductor chip of the second layer (“In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured. On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by claim 1 of US 12,185,012 be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 4, and as applied to claim 2 above, claim 1 of US 12,185,012 does not explicitly teach the first and second manufacture scale technologies.
Murai further teaches that a first manufacture cost for the first manufacture scale technology is different from a second manufacture cost for the second manufacture scale technology (“On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by claim 1 of US 12,185,012 be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 5, and as applied to claim 4 above, claim 1 of US 12,185,012 does not explicitly teach the first and second manufacture scale technologies.
Murai further teaches that the first manufacture cost is lower than the second manufacture cost (“On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor chips of the second and third layers taught by claim 1 of US 12,185,012 be configured according to different manufacture scale technologies as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Consider claim 9, and as applied to claim 1 above, claim 1 of US 12,185,012 further teaches the analog component and the digital component of the analog-to-digital converter are configured to cooperate to perform a conversion operation for a same pixel signal (“an analog-digital conversion unit including an analog circuit and a digital circuit, the analog circuit being configured to convert an analog pixel signal read from respective pixels of the pixel array through a signal line into a digital pixel signal, the digital circuit being configured to receive the digital pixel signal from the analog circuit”).
Claim 1 of US 12,185,012 does not explicitly teach that the first manufacture scale technology and the second manufacture scale technology are respectively configured based on performance requirements of the respective analog component and digital component.
Murai further teaches that the first manufacture scale technology and the second manufacture scale technology are respectively configured based on performance requirements of the respective analog component and digital component (“The image sensor 140 and the image processing chip 240 can be manufactured by different processes, so it is possible to select an optimum process for the respective semiconductor chips. In an example, the image processing chip 240 includes a digital circuit as a main component, which necessitates a large circuit scale and high speed operation. Thus, a miniaturized complementary metal-oxide-semiconductor (CMOS) technology is applied and it is manufactured. On the other hand, the image sensor 140 includes an analog circuit for amplifying and outputting photoelectrically converted electrical signals as a main component, so there is not necessary for high-speed CMOS technology unlike the image processing chip 240, and it can be manufactured by low cost technology.” paragraph 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first manufacture scale technology and the second manufacture scale technology of the respective analog component and digital component taught by the combination of Claim 1 of US 12,185,012 and Murai be based on performance requirements as taught by Murai for the benefit that the overall manufacturing cost can be reduced while maintaining the necessary performance (Murai, paragraph 0048).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
Prosecution Insights