DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325).
Regarding claim 1, Shin teaches a positive temperature coefficient (PTC) circuit protection device (IC device) (fig. 6) comprising: a substrate layer (50); first and second high resistance layers (Rc, Rc) disposed on a top surface (58) of the substrate layer in a spaced apart (i.e., spaced apart by numeral 54) relationship to define a gap (gap 54) therebetween (implicit, as seen in fig. 6); a PTC layer (Rd) disposed on the top surface of the substrate layer (implicit, as seen in fig. 6), in the gap and in contact with the first and second high resistance layers (implicit, as seen in fig. 6); a mask layer (56) covering a top surface (56) of the PTC layer and portions of top surfaces of the first and second high resistance layers (implicit, as seen in fig. 6); an electrically conductive first terminal (i.e., Left/Right terminals 60) covering a first longitudinal end (60) of the substrate layer and an outermost end (60) of the first high resistance layer distal from the PTC layer (implicit, as seen in fig. 6); and an electrically conductive second terminal (60) covering a second longitudinal end (60) of the substrate layer and an outermost end (60) of the second high resistance layer distal from the PTC layer (implicit, as seen in fig. 6).
Shin does not teach a dielectric substrate.
Zhao teaches in a similar field of endeavor in integrated thermal protection devices (i.e., IC device 44) (fig. 3B); wherein a dielectric substrate (44A) (e.g., PTC heater 50 is printed onto first dielectric layer 44A; para. [0033]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the dielectric substrate in Shin, as taught by Zhao, as it provides the advantage of optimizing the circuit design.
Regarding claim 2, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Shin further teaches the device; wherein the electrically conductive first terminal extends onto an exposed portion (60) of the top surface of the first high resistance layer and wherein the electrically conductive second terminal extends onto an exposed portion (60) of the top surface of the second high resistance layer (implicit, as seen in fig. 6).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325) and further in view of Khatua et al (US Publication No. 20080009572).
Regarding claim 3, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Neither Shin nor Zhao teaches wherein the PTC layer has a trip temperature in a range of 50 degrees Celsius to 220 degrees Celsius.
Khatua teaches in a similar field of endeavor in integrated thermal protection devices (i.e., plot PTC device 10) (fig. 1); wherein the PTC layer has a trip temperature in a range of 50 degrees Celsius to 220 degrees Celsius (i.e., a suitable trip temperature of the composition can be in range of 50 degrees Celsius to 220 degrees Celsius; para. [0068]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the PTC trip temperature setting in Shin, as taught by Khatua, as it provides the advantage of optimizing the circuit design.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325) and further in view of Fan et al (US Patent No. 9627722).
Regarding claim 4, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Neither Shin nor Zhao teaches wherein a quantity of PTC material in the PTC layer is in a range of 0.1 milligrams to 1 milligram.
Fan teaches in a similar field of endeavor in integrated thermal protection devices (i.e., PTC device 12) (fig. 1); wherein a quantity (loading of PTC film; Col. 11 lines 18+) of PTC material in the PTC layer is in a range of 0.1 milligrams to 1 milligram (i.e., In certain embodiments, the PTC film has a loading of about 0.1 mg/cm.sup.2, about 0.25 mg/cm.sup.2, about 0.5 mg/cm.sup.2, about 1 mg/cm.sup.2, about 1.5 mg/cm.sup.2, about 2 mg/cm.sup.2, or about 5 mg/cm.sup.2; Col. 11 lines 18+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the PTC material composites setting in Shin, as taught by Fan, as it provides the advantage of optimizing the circuit design.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325) and further in view of Middleman et al (US Patent No. 4413301).
Regarding claim 5, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Neither Shin nor Zhao teaches wherein the first and second high resistance layers are formed of a material having an electrical resistivity in a range of 10^0 Ohm to 10^3 Ohm.
Middleman teaches in a similar field of endeavor in integrated thermal protection devices (i.e., PTC device 25) (fig. 8); wherein the first (resistor 12) and second (resistor 22) high resistance layers are formed of a material (the material of the telephone line) having an electrical resistivity (ohmic value) in a range of 100 Ohm/ to 103 Ohm/ (i.e., resistor 12 has a resistance value from 40 to 500 ohms, and resistor 22 has a resistance value about 200 ohms) (e.g., When the telephone is in use, relays 14 and 15 are open, and lines 14 and 15 are connected via relays 20 and 21 to the supervisory circuit of the telephone exchange, which includes two resistors 22 and 23 each typically having a resistance of about 200 ohms and a battery 24, which typically has a voltage of about 50 volts. PTC protective devices 25 and 26 are in series with relays 20 and 21 respectively; Col. 16 lines 8+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the first and the second resistors ohmic value setting in Shin, as taught by Middleman, as it provides the advantage of optimizing the circuit design.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325) and further in view of Su (US Publication No. 20100181207).
Regarding claim 6, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Neither Shin nor Zhao teaches wherein the first and second high resistance layers are metal foils formed of nickel-phosphorus plated with copper.
Su teaches in a similar field of endeavor in integrated thermal protection devices (i.e., resistors chip) (fig. 4(i)); wherein the first and second high resistance layers (61) are metal foils (i.e., metal foils; para. [0006]) formed of nickel-phosphorus (i.e., nickel-phosphorus; para. [0024]) plated with copper (i.e., plated with copper; para. [0008]) (e.g., the technology for embedded resistors using nickel-silicide-plated copper foil use the same technological process as the conventional printed circuit board fabrication methods; para. [0008]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the first and the second resistors fabrication materials in Shin, as taught by Su, as it provides the advantage of optimizing the circuit design.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325) and further in view of Chen (US Publication No. 20060286742).
Regarding claim 7, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Neither Shin nor Zhao teaches wherein the first and second high resistance layers are metal foils formed of nickel-chromium alloy.
Chen teaches in a similar field of endeavor in integrated thermal protection devices (i.e., resistors chip) (fig. 11); wherein the first and second high resistance layers (5) are metal foils formed of nickel-chromium alloy (i.e., metal foils formed of nickel-chromium alloy; para. [0029]) (e.g., metal foil resistor layer 5 is formed from any resistive material known in the art of metal foil resistor fabrication, for example, nickel-chromium alloy materials, nickel-chromium-aluminum alloy materials, manganese-copper alloy materials, nickel-chromium alloy materials, and higher order alloys of the forgoing resistive materials; para. [0029]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the first and the second resistors fabrication materials in Shin, as taught by Chen, as it provides the advantage of optimizing the circuit design.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US Publication No. 20060163666) in view of Zhao et al (US Publication No. 20200015325) and further in view of Ikeda et al (US Patent No. 6481094).
Regarding claim 8, Shin in view of Zhao and the teachings of Shin as modified by Zhao have been discussed above.
Neither Shin nor Zhao teaches wherein the mask layer is formed of epoxy.
Ikeda teaches in a similar field of endeavor in integrated thermal protection devices (i.e., PTC device) (fig. 13(c)); wherein the mask layer (76) is formed of epoxy (i.e., epoxy; Col. 11 lines 13+) (e.g., although the polyester base thermo-setting resin was used for the protective coating 75 also serving as plating resist, and the plating resist 76 for masking, in the present exemplary embodiment, any other kind of epoxy based resin may also be used, as it is superior in its properties of heat resistance, chemical resistance, and adhesion, as described in the foregoing third and the fourth exemplary embodiments; Col. 11 lines 13+). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the epoxy mask in Shin, as taught by Ikeda, as it provides the advantage of optimizing the circuit design.
Claims 9-20 are not elected.
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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