DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-8 and 10-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Furukawa et al. (US Publication 2021/0082630).
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Figure 1 of Furukawa with Examiner’s Comments (Figure 1EC)
In re claim 1, Furukawa discloses a capacitor array comprising:
a plurality of capacitor portions (10A, 10B, 10C – Figure 1, ¶55) arranged in a plane direction or plane directions orthogonal to a thickness direction (Figure 1); and
a sealing portion (11a, 11b, 12a, 12b – Figure 1EC, ¶60, ¶66, ¶68; Note that each of the sealing layers may be a plurality of layers.) enclosing the plurality of capacitor portions so as to cover opposed main surfaces of the plurality of capacitor portions (Figure 1), wherein the sealing portion includes a plurality of sealing layers (11a, 11b, 12a, 12b – Figure 1) laminated in the thickness direction (Figure 1), and the plurality of sealing layers include:
a first sealing layer (11a, 12a – Figure 1EC) proximal to the capacitor portions (10A, 10B, 10C – Figure 1) in the thickness direction, and containing a first insulating material (¶66);
and second sealing layers (11b, 12b – Figure 1EC) on opposite respective sides of the first sealing layer (11a, 12a – Figure 1) relative to the capacitor portions in the thickness direction and forming two main surfaces of the sealing portion opposed to each other in the thickness direction (Figure 1EC), and containing a second insulating material (¶66).
In re claim 2, Furukawa discloses the capacitor array according to claim 1, as explained above. Furukawa further discloses wherein each of the capacitor portions include:
an anode plate (21 – Figure 1, ¶55) including a porous layer (22 – Figure 1, ¶55) on at least one main surface of two main surfaces of the anode plate opposed to each other in the thickness direction (Figure 1);
a dielectric layer (23 – Figure 1, ¶55) on a surface of the porous layer (22 – Figure 1); and
a cathode layer (24 – Figure 1, ¶55) on a surface of the dielectric layer (23 – Figure 1).
In re claim 3, Furukawa discloses the capacitor array according to claim 1, as explained above. Furukawa further discloses wherein the first insulating material (insulating material of 11a, 12a – Figure 1) contains an insulating resin (¶66).
In re claim 4, Furukawa discloses the capacitor array according to claim 3, as explained above. Furukawa further discloses wherein the first insulating material (insulating material of 11a, 12a – Figure 1EC) further contains inorganic fillers (¶66).
In re claim 6, Furukawa discloses the capacitor array according to claim 1, as explained above. Furukawa further discloses wherein the second insulating material (insulating material of 11b, 12b – Figure 1) contains an insulating resin (¶66).
In re claim 7, Furukawa discloses the capacitor array according to claim 1, as explained above. Furukawa further discloses wherein the first insulating material (insulating material of 11a, 12a – Figure 1EC) and the second insulating material (insulating material of 11b, 12b – Figure 1EC) contain different insulating resins (¶66; Note that the sealing layers can be made of different insulating materials. 11a would contain a different material than 12b, and 11b would contain a different material than 12a.).
In re claim 8, Furukawa discloses the capacitor array according to claim 6, as explained above. Furukawa further discloses wherein the second insulating material (insulating material of 11b, 12b – Figure 1EC) further contains inorganic fillers (¶66).
In re claim 10, Furukawa discloses the capacitor array according to claim 1, as explained above. Furukawa does not disclose wherein a coefficient of linear expansion of the second sealing layers (11, 12 – Figure 1) in the thickness direction is lower than a coefficient of linear expansion of the first sealing layer (30 – Figure 1, ¶59) in the thickness direction (¶66-67). Note that the Examiner is taking the second sealing layers to be elements 11 and 12 here, while the first sealing layer is element 30. All sealing layers can be made from the same resin (¶66). Furthermore, Sealing layers 11 and 12 contain an inorganic filler, such as silica (¶66), which lower the coefficient of linear expansion. Insulating layer 30 does not contain an inorganic filler (¶66).
In re claim 11, Furukawa discloses the capacitor array according to claim 1, as explained above. Furukawa further discloses wherein the first sealing layer (11a, 12a – Figure 1EC) includes first insulation portions (any arbitrary portion of 11a, 12a near 10A, 10B, 10C – Figure 1EC) each covering a corresponding one of the two main surfaces of the plurality of capacitor portions (10A, 10B, 10C – Figure 1EC).
In re claim 12, Furukawa discloses the capacitor array according to claim 11, as explained above. Furukawa further discloses wherein in a region of the sealing portion (11a, 12a, 11b, 12b – Figure 1EC) on one main surface side (upper surface of 10A, 10B, 10C – Figure 1EC) of the two main surfaces of the sealing portion (Figure 1EC), a maximum dimension of a corresponding one of the first insulation portions (any arbitrary portion of 11a, 12a – Figure 1EC) of the first sealing layer (11a, 12a – Figure 1EC) in the thickness direction and a maximum dimension of a corresponding one of the second sealing layers (11b, 12b – Figure 1EC) in the thickness direction differ from each other (Figure 1EC; Note that the Examiner is arbitrarily taking the first insulating portion to have a greater maximum thickness than the second sealing layer.).
In re claim 13, Furukawa discloses the capacitor array according to claim 12, as explained above. Furukawa further discloses wherein in the region of the sealing portion (11a, 12a, 11b, 12b – Figure 1EC) on one main surface side (upper surface of 10A, 10B, 10C – Figure 1EC) of the two main surfaces of the sealing portion (Figure 1EC), a maximum dimension of a corresponding one of the first insulation portions (any arbitrary portion of 11a, 12a – Figure 1EC) of the first sealing layer (11a, 12a – Figure 1EC) in the thickness direction is larger than the maximum dimension of the corresponding one of the second sealing layers (11b, 12b – Figure 1EC) in the thickness direction. (Figure 1EC; Note that the Examiner is arbitrarily taking the first insulating portion to have a greater maximum thickness than the second sealing layer.).
In re claim 14, Furukawa discloses the capacitor array according to claim 13, as explained above. Furukawa further discloses wherein in the region of the sealing portion (11a, 12a, 11b, 12b – figure 1EC) on the one main surface side (upper surface of 10A, 10B, 10C – Figure 1EC) of the two main surfaces of the sealing portion, a ratio of the maximum dimension of the corresponding one of the first insulation portions (any arbitrary portion of 11a, 12a – Figure 1EC) of the first sealing layer (11a, 12a – Figure 1EC) in the thickness direction to the maximum dimension of the corresponding one of the second sealing layers (11b, 12b – Figure 1EC) in the thickness direction is 110% or more (Figure 1EC; Note that the Examiner is arbitrarily taking the first insulating portion to have a greater maximum thickness than the second sealing layer. Furthermore, the thickness of 11b and 12b can be arbitrarily chosen.).
In re claim 15, Furukawa discloses the capacitor array according to claim 13, as explained above. Furukawa further discloses wherein in the region of the sealing portion (11a, 12a, 11b, 12b – Figure 1EC) on the one main surface side (upper surface of 10A, 10B, 10C – Figure 1EC) of the two main surfaces of the sealing portion, the maximum dimension of the corresponding one of the first insulation portions (any arbitrary portion of 11a, 12a – Figure 1EC) of the first sealing layer in the thickness direction is 5 μm or more (Figure 1EC; Note that the Examiner is arbitrarily taking the first insulating portion with the required thickness to meet this limitation.).
In re claim 16, Furukawa discloses the capacitor array according to claim 13, as explained above. Furukawa further discloses wherein in the region of the sealing portion (11a, 12a, 11b, 12b – Figure 1EC) on the one main surface side (upper surface of 10A, 10B, 10C – Figure 1EC) of the two main surfaces of the sealing portion, the maximum dimension of the corresponding one of the second sealing layers (11b or 12b – Figure 1EC) in the thickness direction is 100 μm or less (Figure 1EC; Note that the Examiner is arbitrarily adjusting the thickness of 12b to meet this thickness limitation.).
In re claim 17, Furukawa discloses the capacitor array according to claim 13, as explained above. Furukawa further discloses wherein in the region of the sealing portion (11a, 12a, 11b, 12b – Figure 1EC) on the one main surface side (upper surface of 10A, 10B, 10C – Figure 1EC) of the two main surfaces of the sealing portion, a ratio of a minimum dimension of the corresponding one of the first insulation portions (any arbitrary portion of 11a, 12a – Figure 1EC) of the first sealing layer in the thickness direction to the maximum dimension of the corresponding one of the first insulation portions (any arbitrary portion of 11a, 12a having a larger thickness than an arbitrary portion of 11a, 12a having a smaller thickness – Figure 1EC) of the first sealing layer in the thickness direction is 50% or less (Figure 1EC; Note that the insulating portion can arbitrarily have two thicknesses in which one part has a thickness that is 50% or less than another thickness.).
In re claim 18, Furukawa discloses the capacitor array according to claim 11, as explained above. Furukawa further discloses wherein the first sealing layer (11a, 12a – Figure 1EC) further includes a second insulation portion (portion of 11a, 12a that passes with a thickness of D10 – Figure 1EC, ¶64) separating each of the plurality of capacitor portions (10A, 10B, 10C – Figure 1EC) from each other (Figure 1EC).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furukawa et al. (US Publication 2021/0082630) in view of Toshihiko et al. (JPH0945591A).
In re claim 5, Furukawa discloses the capacitor array according to claim 4, as explained above. Furukawa does not disclose wherein a median diameter D50 of the inorganic fillers in the first insulating material is 10 μm or less.
Toshihiko discloses wherein a median diameter D50 of the inorganic filler (¶26) an encapsulating insulating material (5 – Figure 2, ¶9) is 10 μm or less (¶26).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the particle size of the filler as described by Toshihiko to provide for improved oxygen-blocking and ESR characteristics (¶26: Toshihiko).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furukawa et al. (US Publication 2021/0082630) in view of Masashi (JP2011029623A).
In re claim 9, Furukawa discloses the capacitor array according to claim 6, as explained above. Furukawa does not disclose wherein the second insulating material further contains a glass cloth.
Masashi discloses wherein the insulating material (8 – Figure 4, Figure 5, ¶42) contains a glass cloth (¶42).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the glass cloth filler to realize a device having desired mechanical strength.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furukawa et al. (US Publication 2021/0082630) in view of Kazuaki et al. (JP2008078301A).
In re claim 19, Furukawa discloses the capacitor array according to claim 11, as explained above. Furukawa further discloses a through-electrode that may be implemented in a capacitor array for a composite electronic component wherein an electronic component is mounted on the capacitor array (¶86).
Furukawa does not disclose wherein the first sealing layer further includes third insulation portions each passing through the corresponding one of the plurality of capacitor portions in the thickness direction
Kazuaki does not disclose wherein the sealing layer (15 or 16 – Figure 1, ¶29, ¶30) further includes third insulation portions (portions of either 15 or 16 around 19 – Figure 1, ¶36) each passing through the corresponding one of the plurality of capacitor portions (22 – Figure 1, ¶16) in the thickness direction (Figure 1).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the third insulation portion and through-electrode as described by Kazuaki to provide for a signal line, and thus, allow the capacitor to act as an interposer.
In re claim 20, Furukawa discloses the capacitor array according to claim 11, as explained above. Furukawa further discloses a through-electrode that may be implemented in a capacitor array for a composite electronic component wherein an electronic component is mounted on the capacitor array (¶86).
Furukawa does not disclose comprising through-hole conductors each respectively passing through the corresponding one of the capacitor portions and the sealing portion in the thickness direction.
Kazuaki discloses comprising through-hole conductors (19 – Figure 1) each respectively passing through the corresponding one of the capacitor portions (22 – Figure 1) and the sealing portion (15 or 16 – Figure 1) in the thickness direction (Figure 1).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the third insulation portion and through-electrode as described by Kazuaki to provide for a signal line, and thus, allow the capacitor to act as an interposer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miki et al. (US Patent 6,785,147) Figure 4
Takatani et al. (US Publication 2007/0285876) [¶45]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARUN RAMASWAMY/Primary Examiner, Art Unit 2847
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