DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/27/2026 have been fully considered but they are not persuasive. Applicant’s arguments are summarized as:
Prior art of record, Suarez, does not disclose pre-emptively moving a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource.
Examiner notes that Suarez clearly shows the tasks dependencies in figure 1 (arrows indicate dependencies - how data produced by one task is used by another task; i.e. task A produces data used by tasks B, C, and D). Suarez further shows shared buffers 254a-n in figure 2, is used to store the results of each task, and the results are then used by other processors for dependent tasks (e.g. CPU processes task A and places results in buffer 254a, that DSP and GPU then access for tasks B and C; shown in figure 2).
Having responded to all of applicant’s arguments, examiner notes that prior art of record still provide a valid ground of rejection, updated below to reflect the above arguments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 2, 4-6, 8, 9, 11-13, 15, 16, 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8 and 15 recite “pre-emptively”, and it is unclear what action is being avoided or anticipated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4-6, 8, 9, 11-13, 15, 16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kluchnikov (pub # US 20160092367 A1) in view of Suarez Garcia (pub # US 20170060633 A1).
Regarding claim 1, Kluchnikov discloses an apparatus (system shown in figure 1, details of multiple core version shown in figure 7), comprising: processing circuitry (processors shown in figure 8 comprised of multiple cores shown in figure 7, paragraph 21; paragraph 67) coupled to a memory (memory system, including the shared cache units 706, figure 7), the processing circuitry including a first processing resource and a second processing resource (any two of the multiple cores 702A-N), the processing circuitry to: preemptively (there is no teaching that the data must be first requested) move a data output from the one or more producer tasks executing on the first processing resource to a cache memory (memory system, including the shared cache units 706, shown in figure 7) communicatively coupled to the second processing resource (coordinate and operate the cores, paragraph 70; two or more cores execute the same instruction set with data sharing of the two processors through the shared cache, paragraph 69, processors using point-to-point interface to exchange data, using shared cache explained in paragraphs 80-82).
Kluchnikov discloses data dependencies, does not disclose explicitly transmitting and receiving data dependencies. However, Garcia discloses receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource (dependent tasks, transfer data for use by a second task from different data buffers to different processors, paragraph 48, the tasks later in the chain of tasks depend on results of previous tasks, and would be consumer tasks, figure 1; the sharing of buffers between different processors executing different tasks is shown in figure 2). Furthermore, teachings of Kluchnikov and Garcia are both directed to processor design.
Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Kluchnikov with Garcia by using information on data dependencies in the processor system of Kluchnikov for the benefit of correctly and efficiently pass data amongst tasks and processors that depend on each other.
Regarding claim 2, the above combination discloses the apparatus of claim 1, the apparatus of claim 1, wherein the one or more tasks are represented in a task graphs as tasks connected by an edge, wherein the one or more tasks map to the processing resources (task graphs with dependencies shown in figure 2A, task distribution to processing resources graph shown in figure 2B; paragraph 48, Garcia).
Regarding claim 4, the above combination discloses the apparatus of claim 4, wherein the processing circuitry to enqueue a kernel for execution by one of the processing resources (queue storing instruction and information corresponding to instructions, paragraph 23).
Regarding claim 5, the above combination discloses the apparatus of claim 2, wherein the processing circuitry to pass one or more destination identifiers for the one or more tasks to the processing resources (transfer heuristic data including destination identity, Garcia, paragraph 5, 34).
Regarding claim 6, the above combination discloses the apparatus of claim 21, wherein the cache memory comprises a first level cache (L1 cache, Kluchnikov, paragraph 21), and wherein the first level cache is shared between multiple processing resources (Kluchnikov, “data cache may be shared by multiple cores of a processor”, paragraph 21), wherein the processing circuitry includes one or more graphics processing circuitry or application processing circuitry (GPU, DSP, figure 2B, Garcia).
Claims 8, 9, 11-13, 15, 16, 18-20 are substantially similar to claims 1, 2, 4-6 above. The same grounds of rejection are applied.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181
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