DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: “the third switch is connected between the first circuit and the second node” should be “the third switch is connected between the first circuit and a second node”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-11 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ku (US 2015/0188518).
For claim 1, Ku teaches a device (Figures 2-3) comprising:
a function circuit (310, 320) including a plurality of semiconductor devices (P1, N1, P2, N2); and
a body bias generator (410, 420, 100) configured to provide body bias voltages (VPR, VBBN) to body terminals of the plurality of semiconductor devices (as understood by examination of Figures 2-3), wherein the function circuit comprises:
a first circuit (310);
a second circuit (320); and
first to fourth switches (first: S1 and S4, second: S5 and S8, third: S2 and S3, fourth: S6 and S7), wherein
the first switch is connected between the first circuit (body terminal of P1) and a first node (node at the output of 410) to which the body bias voltage is applied (VPR), and
the second switch is connected between the second circuit (body terminal of P2) and the first node (VPR, as understood by examination of Figures 2-3),
the third switch is connected between the first circuit and the second node (node carrying VPP) to which a supply voltage is applied (as understood by examination of Figures 2-3), and
the fourth switch is connected between the second circuit and the second node (as understood by examination of Figures 2-3).
For claim 2, Ku further teaches:
the plurality of semiconductor devices include a P-type transistor (P1, P2) and an N-type transistor (N1, N2).
For claim 5, Ku further teaches that the body bias generator is configured to:
increase a positive body bias voltage level provided to a body terminal of the P-type transistor (VPP is higher than VPR, [25]); and
reduce a negative body bias voltage level provided to a body terminal of the N-type transistor (VBBN is lower than VSS, [26]).
For claim 6, Ku further teaches that:
the switch control signal includes a first switch control signal (HC1, LC2), a second switch control signal (HC3, LC4), and a third switch control signal (HC2, LC1).
For claim 7, Ku further teaches that:
the second switch and the third switch are configured to be turned on based on the first switch control signal being in a high state, so as to provide the body bias voltage to body terminals of the plurality of semiconductor devices included in the second circuit (capable of, since 310 and 320 are independently controllable into either the first or second operation mode, as understood by examination of Figure 4 and [20]).
For claim 8, Ku further teaches that:
the first switch and the fourth switch are configured to be turned on based on the second switch control signal being in a high state, so as to provide the body bias voltage to body terminals of the plurality of semiconductor devices included in the first circuit (capable of, since 310 and 320 are independently controllable into either the first or second operation mode, as understood by examination of Figure 4 and [20]).
For claim 9, Ku further teaches that:
the third switch and the fourth switch are configured to be turned on based on the third switch control signal being in a high state, so as to provide the supply voltage to a plurality of semiconductor devices included in the first circuit and a plurality of semiconductor devices included in the second circuit (capable of, since 310 and 320 are independently controllable into either the first or second operation mode, as understood by examination of Figure 4 and [20]).
For claim 10, Ku teaches a memory device comprising:
a function circuit (310, 320) including a plurality of semiconductor devices (P1, N1, P2, N2); and
a body bias generator (410, 420, 100) configured to provide body bias voltages (VPR, VBBN) to body terminals of the plurality of semiconductor devices (as understood by examination of Figures 2-3), wherein the function circuit comprises:
a first circuit (310);
a second circuit (320); and
a first switch (S1 and S4) and a second switch (S2 and S3), wherein
the first switch is connected between the first circuit (body terminal of P1) and a first node (node at the output of 410) to which the body bias voltage is applied (VPR),
the second switch is connected between the first circuit and the second node (node carrying VPP) to which a supply voltage is applied (as understood by examination of Figures 2-3), and
the second circuit is also connected to the second node (via S6).
For claim 11, Ku further teaches:
the first circuit operates only in a power-up mode operation, the second circuit is configured to operate in a normal mode operation including the power-up mode (capable of, [20]), and the plurality of semiconductor devices include a PMOS device and an NMOS device (as understood by examination of Figure 3).
For claim 16, Ku further teaches that:
the first switch and the second switch are operable to turn on in an alternating manner (as understood by examination of the Figures and [20]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-4 and 13-15, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ku in view of official notice.
For claims 3-4, Ku teaches:
a signal generation circuit (100) configured to generate a switch control signal for controlling the first to fourth switches (as understood by examination of Figures 2-3);
a DC power supply (VDD) used to generate a positive body bias voltage (VPR) to a body terminal of the P-type transistor (as understood by examination of Figure 6) and the charge pump to provide a negative body bias voltage to a body terminal of the N-type transistor (VBBN, as understood by examination of Figure 7) but fails to teach the charge pump generating the positive body bias voltage as claimed.
However, examiner takes official notice that a charge pump is a well-known type of DC/DC converter.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to generate VDD from an external voltage by using a charge pump as a DC/DC converter for the advantages of charge pumps when compared to other types of DC/DC converters (e.g., low noise and compact design).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
The combination of Ku and official notice teaches:
the charge pump is configured to: provide a positive body bias voltage to a body terminal of the P-type transistor (VPR is selected from either VINT or VDD, VINT is based on VDD which is the output of the charge pump).
For claims 13, Ku teaches:
a signal generation circuit (100) configured to generate a switch control signal for controlling the first and second switches (as understood by examination of Figures 2-3);
a DC power supply (VDD) used to generate a positive body bias voltage (VPR) to a body terminal of the P-type transistor (as understood by examination of Figure 6) and the charge pump to provide a negative body bias voltage to a body terminal of the N-type transistor (VBBN, as understood by examination of Figure 7) but fails to teach the charge pump generating the positive body bias voltage as claimed.
However, examiner takes official notice that a charge pump is a well-known type of DC/DC converter.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to generate VDD from an external voltage by using a charge pump as a DC/DC converter for the advantages of charge pumps when compared to other types of DC/DC converters (e.g., low noise and compact design).
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
The combination of Ku and official notice teaches:
the charge pump is configured to: provide a positive body bias voltage to a body terminal of the P-type transistor (VPR is selected from either VINT or VDD, VINT is based on VDD which is the output of the charge pump).
For claim 14, the combination of Ku and official notice teaches the limitations of claim 13 as cited above and Ku further teaches that:
the switch control signal comprises a first switch control signal (HC1, LC2) and a second switch control signal (HC2, LC1), and the first switch control signal and the second switch control signal are complementary (as understood by examination of the Figures and [20]).
For claim 15, the combination of Ku and official notice teaches the limitations of claim 13 as cited above and Ku further teaches that:
the body bias voltage comprises a positive body bias voltage (VPR) and a negative body bias voltage (VBBN), and the positive body bias voltage is applied to a PMOS device body terminal, and the negative body bias voltage is applied to an NMOS device body terminal (as understood by examination of Figure 3).
For claim 17, the combination of Ku and official notice teaches the limitations of claim 14 as cited above and Ku further teaches that:
the second switch is operable to turn on based on the first switch control signal, such that the supply voltage is provided to the plurality of semiconductor devices included in the first circuit and to the plurality of semiconductor devices included in the second circuit (as understood by examination of the Figures and [20]).
For claim 18, the combination of Ku and official notice teaches the limitations of claim 14 as cited above and Ku further teaches that:
the first switch is operable to turn on based on the second switch control signal, such that the body bias voltage is provided to the body terminals of the plurality of semiconductor devices included in the first circuit (as understood by examination of the Figures and [20]).
Claim(s) 12 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ku in view of Yamada (US 2006/0023544)
For claim 12, Ku teaches the limitations of claim 11 as cited above but fails to teach a training circuit and a test mode register as claimed.
However, Yamada teaches a training circuit (224) configured to perform a training operation (instruction code IC); a test mode register (226, Figure 7) configured to store test operation information (C1, Figure 7); and
a memory cell array (116) including a plurality of memory cells (as understood by examination of Figure 7).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to control the back gate of the transistors within Yamada’s training circuit, test mode register and memory cell array by using Ku’s back bias control such that the training circuit and/or test mode register correspond to Ku’s first circuit and the memory cell array correspond to Ku’s second circuit for the advantages described in Ku’s [5].
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of invention.
For claim 19, Ku teaches a device (Figures 2-3) comprising:
a function circuit (310, 320) including a plurality of semiconductor devices (P1, N1, P2, N2);
a body bias generator (410, 420, 100) configured to provide body bias voltages (VPR, VBBN) to body terminals of the plurality of semiconductor devices (as understood by examination of Figures 2-3), wherein the function circuit comprises:
a first circuit (310);
a second circuit (320); and
first to fourth switches (first: S1 and S4, second: S5 and S8, third: S2 and S3, fourth: S6 and S7), wherein
the first switch is connected between the first circuit (body terminal of P1) and a first node (node at the output of 410) to which the body bias voltage is applied (VPR), and
the second switch is connected between the second circuit (body terminal of P2) and the first node (VPR, as understood by examination of Figures 2-3),
the third switch is connected between the first circuit and the second node (node carrying VPP) to which a supply voltage is applied (as understood by examination of Figures 2-3), and
the fourth switch is connected between the second circuit and the second node (as understood by examination of Figures 2-3).
Ku fails to teach:
a data input/output circuit including a plurality of semiconductor devices and configured to transmit and receive 8-bit data.
However, Yamada teaches a data input/output circuit (Figure 7) including a plurality of semiconductor devices (224, 226, 116) and configured to transmit and receive 8-bit data (I1 and C1 are 8 bit codes, [53]).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to control the back gate of the transistors within the elements of Yamada’s Figure 7 by using Ku’s body bias generator for the advantages described in Ku’s [5].
Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of invention.
For claim 20, the combination of Ku and Yamada teaches the limitations of claim 19 as cited above and Ku further teaches:
the plurality of semiconductor devices comprises a PMOS device (P1, P2) and an NMOS device (N1, N2), the body bias voltage comprises a positive body bias voltage (VPR) and a negative body bias voltage (VBBN), the positive body bias voltage is provided to a PMOS device body terminal (as understood by examination of Figure 3), and the negative body bias voltage is provided to an NMOS device body terminal (as understood by examination of Figure 3), and at least two of the first to fourth switches are operable to turn on based on a switch control signal (output of 100, Figure 2) such that the body bias voltage is provided to the body terminals of the plurality of semiconductor devices included in the first circuit or the second circuit (as understood by examination of Figure 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849