DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-12 in the reply filed on 06/01/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoo et al. (US 6,898,659), hereinafter referred to as Yoo.
Referring to claim 1. Yoo teaches, as claimed, a computing system, comprising: a host (i.e.-host 200, see fig. 1); a memory controller electrically connected with the host through a host bus (i.e.-memory controller 120 connected to the host with bus interface 560 thru PCMCIA 110, see figs. 2 and 3); an interface circuit electrically connected with the memory controller through a first data bus (i.e.-PCMCIA interface 110 connected to memory controller 120 thru 16-bit unit bus, col. 3, lines 58-59); and a memory apparatus electrically connected with the interface circuit through a second data bus (i.e.-external memory 300 connected to PCMCIA interface 110 through 32-bit data bus, col. 2, lines 19-23 and col. 3, lines 53-55), wherein a width of the second data bus is greater than or equal to a width of the first data bus (i.e.-32-bit data bus is greater than 16-bit width bus, col. 5, lines 32-34) (Note: n-bit bus is greater than m-bit unit, col. 3, lines 1-2).
As to claim 3, Yoo innately teaches the computing system of claim 1, wherein the first data bus simultaneously transmits n bits of data (i.e.-PCMCIA interface, 16 bit data, col. 3, lines 58-59), and the second data bus simultaneously transmits m bits of data, where n is a multiple of 2, and m is equal to n or is a multiple of n (i.e.-bus 160, 32 bits, col. 3, lines 53-54&57).
As to claim 5. Yoo innately teaches the computing system of claim 1, wherein the first data bus is one of a parallel bus and a partial parallel bus, and the second data bus is a parallel bus (col. 3, lines 11-14; and col. 4, lines 10-12).
As to claim 6, Yoo teaches the computing system of claim 1, wherein a data bandwidth of the first data bus is substantially the same as a data bandwidth of the second data bus (i.e.-in a single transfer mode, the bandwidth of bus interface 560 is the same – 16 bits – as the bus 160 of the external memory, col. 5, lines 45-48 and 52-54).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Chiu et al. (US 7,958,285), hereinafter referred to as Chiu.
As to claims 2 and 4, Yoo teaches the claimed invention except the limitations of claims 2 and 4.
On the other hand, Chiu discloses a method and system for transferring data between a processor core and an I/O device with different clock domains, wherein a clock rate of the second data bus is less than or equal to a clock rate of the first data bus (col. 2, lines 34-39 and 40-43); and wherein a ratio of clock frequencies of the first data bus to the second data bus is set to one of 1:1, 2:1, and 4:1 (col. 2, lines 44-48).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art, to modify the teachings of Yoo so that: a clock rate of the second data bus is less than or equal to a clock rate of the first data bus; and a ratio of clock frequencies of the first data bus to the second data bus is set to one of 1:1, 2:1, and 4:1, as taught by Chiu. The motivation for doing so would have been to deterministically transfer data between a processor and an I/O domain, thereby accurately transferring data by avoiding a skew caused by variation of clocks between two data paths/buses.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of McElheny et al. (US 10,291,397), hereinafter referred to as McElheny.
As to claims 7 and 8, Yoo teaches the claimed invention except the limitations of claims 7 and 8.
On the other hand, McElheny discloses a system comprised of an integrated circuit package including a package substrate and an active interposer; wherein memory elements are disposed on the interposer (col. 1, lines 51-53 and 57-58), while the host processor is externally coupled to the package via separate communication path (see fig. 3 and col. 6, lines 25-26).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art, to modify the teachings of Yoo so that the memory controller, the interface circuit, and the memory apparatus are disposed on the same interposer and the host is not; and wherein the memory controller, the interface circuit, and the memory apparatus are disposed on the same substrate and the host is not, as taught by McElheny. The motivation for doing so would have been to embed memory elements and accelerator processors in one IC package, thereby enhancing processing efficiency by reducing latencies.
As to claims 9-12, Yoo teaches the claimed invention, as discussed in claim 1, except the limitations of claims 9-12. It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to modify the teachings of Yoo so that: 9. the host, the memory controller, and the interface circuit are disposed on the same interposer and the memory apparatus is not; 10. the host, the memory controller, and the interface circuit are disposed on the same substrate and the memory apparatus is not; 11. the host, the memory controller, the interface circuit, and the memory apparatus are disposed on the same interposer; and 12. the host, the memory controller, the interface circuit, and the memory apparatus are disposed on the same substrate; since it has been held that rearranging parts/components of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Examiner’s note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Halbert et al. (US 6,742,098), Randell et al. (US 7,552,267), Tsai (US 9,076,506), Sakaue et al. (US 11,500,793), Bonella et al. (US 5,404,559), and Linnen et al. (US 10,242,750) do teach interface device having variable data transfer mode between high-speed bus and low-speed bus.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184
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