DETAILED ACTION
This Office Action is in response to an application that was filed on 11/21/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
The disclosure is objected to because of antecedent errors:
The limitation phrase “power supply” does not have the proper antecedent basis in claim 4, since the cited limitation phrase has already established antecedent phrase in independent claim 1.
The limitation phrase “current carrying layer” does not have the proper antecedent basis in claim 7, since the cited limitation phrase has never established antecedent basis.
Appropriate correction is required as well as no new matter should be entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (CN111065199A and Liu hereinafter, cited in the following: 11/21/2024 IDS; 08/16/2023 Written Opinion of the International Searching Authority; 05/27/2023 Chinese First Office Action for Application 202211049239.9; 09/28/2023 Chinese Second Office Action for Application 202211049239.9; 08/28/2025 Chinese First Office Action for Application 202411020418.9; and 08/12/2025 European Search Opinion).
Regarding claim 1, Liu discloses a computing node (Figs. 3-4 and ¶[0027-0028 & 0048] from Espacenet Translation shows and indicates computing node of Figs. 3-4 {Fig. 3 is the schematic diagram of the power supply device and Fig. 4 is the top view of the power supply device shown in Fig. 3}), comprising: a mainboard, wherein an electronic component is mounted on a first surface of the mainboard (items 1, 3, 11 of Figs. 3-4 and ¶[0045-0051] from Espacenet Translation shows and indicates mainboard 1 {PCB 1}, where electronic component 3 {chip 3} is mounted on first surface 11 {first side 11} of mainboard 1), a through-current hole is disposed in a thickness direction of the mainboard and electrically connected to the electronic component (item 14 of Fig. 3 and ¶[0046_0048 & 0050] from Espacenet Translation shows and indicates through-current hole 14 {copper pillar/via second flow channel 14} is disposed in the thickness direction of mainboard 1 and electrically connected to electronic component 3); and a current guiding structure disposed on a side of the mainboard and electrically connected to the through-current hole, wherein the current guiding structure is configured to transmit a power supply current output from a power supply to the through-current hole (items 4, 2, 13 of Figs. 3-4 and ¶[0045-0051] from Espacenet Translation shows and indicates current guiding structure 4 {current-carrying module 4} disposed on the side of mainboard 1 and electrically connected to through-current hole 14; where current guiding structure 4 is configured to transmit power supply current output from power supply 2 through copper pillar/via first flow channel 13 to through-current hole 14).
Regarding, claim 4, Liu discloses a computing node, wherein the electronic component comprises a processor module, the mainboard comprises: a high-conductivity part; and a plurality of through-current holes, including a second through-current hole, wherein the second through-current hole extends in the thickness direction of the mainboard, including a first opening connected to the current guiding structure and a second opening connected to the high-conductivity part, and the high-conductivity part extends from the second opening to the first surface of the mainboard in the thickness direction of the mainboard, and is in contact with the power supply end of the processor module (item 31 of Figs. 3-4 and ¶[0040_0046 & 0048-0050] from Espacenet Translation shows and indicates where electronic component 3 is comprised of a processor module {chip device 3 to be powered by the power supply device of Figs. 3-4 may include a central processing unit}; and where mainboard 1 is comprised of high-conductivity part 31 {second pin 31} and the plurality of through-current holes 14 {plurality of copper pillar/via second flow channels 14} including a second through-current hole 14-other; and where second through-current hole 14-other extends in the thickness direction of mainboard 1 that includes first opening 14_4-opening {opening of copper pillar/via second flow channel 14 towards and connecting current-carrying module 4} connected to current guiding structure 4 and a second opening 14_31-opening {opening of copper pillar/via second flow channel 14 towards and connecting second pin 31} connected to high-conductivity part 31; and where high-conductivity part 31 extends from second opening 14_31-opening to first surface 11 of mainboard 1 in the thickness direction of mainboard 1 and is in contact with power supply 2 end of the processor module that is electronic component 3).
Regarding, claim 5, Liu discloses a computing node, wherein a cross-sectional area of the high-conductivity part is greater than or equal to a cross-sectional area of the second through-current hole (Figs. 3-4 and ¶[0040_0046 & 0048-0050] from Espacenet Translation is understood to show where the cross-sectional area of high-conductivity part 31 is greater than or equal to the cross-sectional area of second through-current hole 14-other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Liu, as detailed in the rejection of claim 1 above, and in view of Jafari et al. (US20080106861A1 and Jafari hereinafter), as motivated by Reynov et al. (US10,109,959B1 and Reynov hereinafter).
Regarding, claim 18, Liu discloses a computing node, wherein the mainboard comprises a plurality of units, and a unit comprises a processor; and the units are arranged in an array or sequentially arranged on the mainboard (item 7 of Fig. 5 & Figs. 3-4 and ¶[0040 & 0045-0050] from Espacenet Translation shows and indicates where mainboard 1 is comprised of units of electronic component 3 and second connector 7; and where the unit of electronic component 3 is comprised of a processor {chip device 3 to be powered by the power supply device of Figs. 3-4 may include a central processing unit}; and the units of electronic component 3 and second connector 7 are arranged in an array or sequentially arranged on mainboard 1).
However, Liu does not disclose wherein each computing unit comprises a processor, a memory module disposed on a side of the processor, and a heat sink.
Jafari discloses wherein each computing unit comprises a processor, a memory module disposed on a side of the processor, and a heat sink (items 121, 123, 130, 401, 170 of Fig. 5B and ¶[0032 & 0047] shows and indicates where each computing unit of Fig. 5B is comprises processor 130, a memory module 121 OR 123 disposed on the side of processor 130, and a heat sink 401 {solder balls 401 to conduct most of the heat from the processor 130 directly into the PCB 170, where this provides a heat conduction path for the processor 130 that is independent of the memory components 121 and 123}; therefore, Liu will have a computing node that has the following structures by incorporating the structure of Jafari: the mainboard that is comprised of a plurality of units, where the unit is comprised of a processor; a memory unit that is disposed on the side of a processor; and a heat sink).
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate wherein each computing unit comprises a processor, a memory module disposed on a side of the processor, and a heat sink into the device of Liu. One would have been motivated to take the computing node of Liu and have the computing unit be comprised of a processor, a memory module disposed on a side of the processor, and a heat sink, in order to provide to provide a heat conduction path for the processor that is independent of the memory components while providing a processor-memory devices, as indicated by Jafari in¶[0032 & 0047], and provide the second connector of Liu with a dual connectors with embedded CPU’s with contacts to the PCB, and as further motivated by Reynov in 4:4-19 & 5:20-36 & 6:36-42 & 7:20-38 and Fig. 2, in the computing node of Liu.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cepulis et al. (US20150241940A1 and Cepulis hereinafter), in view of Liu.
Regarding claim 20, Cepulis discloses a computing device (item 100 of Fig. 1 and ¶[0009] shows and indicates computing device 100 {computer system 100}), comprising: a housing and a computing node mounted in the housing (items 118, 102, 104, 106 of Fig. 1 and ¶[0009-0010] shows and indicates housing 118 {enclosure 118} and computing node 102 OR 104 OR 106 {compute nodes 102, 104, 106} mounted in housing 118).
Cepulis discloses the claimed invention except to explicitly disclose wherein the computing node comprises: a mainboard, wherein an electronic component is mounted on a first surface of the mainboard, a through-current hole is disposed in a thickness direction of the mainboard and electrically connected to the electronic component; and a current guiding structure disposed on a side of the mainboard and electrically connected to the through-current hole, wherein the current guiding structure is configured to transmit a power supply current output from a power supply to the through-current hole.
Liu discloses a computing node (Figs. 3-4 and ¶[0027-0028 & 0048] from Espacenet Translation shows and indicates computing node of Figs. 3-4 {Fig. 3 is the schematic diagram of the power supply device and Fig. 4 is the top view of the power supply device shown in Fig. 3}), comprising: a mainboard, wherein an electronic component is mounted on a first surface of the mainboard (items 1, 3, 11 of Figs. 3-4 and ¶[0045-0051] from Espacenet Translation shows and indicates mainboard 1 {PCB 1}, where electronic component 3 {chip 3} is mounted on first surface 11 {first side 11} of mainboard 1), a through-current hole is disposed in a thickness direction of the mainboard and electrically connected to the electronic component (item 14 of Fig. 3 and ¶[0046_0048 & 0050] from Espacenet Translation shows and indicates through-current hole 14 {copper pillar/via second flow channel 14} is disposed in the thickness direction of mainboard 1 and electrically connected to electronic component 3); and a current guiding structure disposed on a side of the mainboard and electrically connected to the through-current hole, wherein the current guiding structure is configured to transmit a power supply current output from a power supply to the through-current hole (items 4, 2, 13 of Figs. 3-4 and ¶[0045-0051] from Espacenet Translation shows and indicates current guiding structure 4 {current-carrying module 4} disposed on the side of mainboard 1 and electrically connected to through-current hole 14; where current guiding structure 4 is configured to transmit power supply current output from power supply 2 through copper pillar/via first flow channel 13 to through-current hole 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the computing node comprises: a mainboard, wherein an electronic component is mounted on a first surface of the mainboard, a through-current hole is disposed in a thickness direction of the mainboard and electrically connected to the electronic component; and a current guiding structure disposed on a side of the mainboard and electrically connected to the through-current hole, wherein the current guiding structure is configured to transmit a power supply current output from a power supply to the through-current hole into the structure of Cepulis. One would have been motivated in the computing device of Cepulis and have the computing node be comprised of the following structures: a mainboard, where the electronic component is mounted on the first surface of the mainboard; through-current hole that is disposed in the thickness direction of the mainboard and electrically connected to the electronic component; current guiding structure that is disposed on the side of the mainboard and electrically connected to the through-current hole, where the current guiding structure is configured to transmit the power supply current output from the power supply to the through-current hole, in order to designed a detail power supply device so as to provide a short transmission current path to the chip(s)/device(s)/CPUs’ in mobile phones, tablets, and handheld computers, as indicated by Liu in the abstract and ¶[0040], in the computing device of Cepulis.
Allowable Subject Matter
Claims 2-3, 6-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the primary reason for allowance is due to a computing node, wherein the mainboard comprises a current carrying layer extending in a cross-sectional direction of the mainboard, and the current carrying layer is electrically connected the through-current hole; and the through-current hole is electrically connected to at least one electronic component via the current carrying layer.
Regarding claims 3, 8-10, and 14, the primary reason for allowance is due to the dependency on claim 2.
Regarding claim 6, the primary reason for allowance is due to a computing node, wherein a cross-sectional area of the high-conductivity part gradually expands in a direction from the second opening of the second through-current hole to the first surface of the mainboard.
Regarding claim 7, the primary reason for allowance is due to a computing node, wherein the second opening of the second through-current hole and the high-conductivity part are connected to each other at a first location of a current carrying layer; and the first location of the current carrying layer is further electrically connected to at least one through-current hole.
Regarding claim 11, the primary reason for allowance is due to the dependency on claim 10.
Regarding claims 12-13, the primary reason for allowance is due to the dependency on claim 8.
Regarding claim 15, the primary reason for allowance is due to a computing node, wherein the current guiding structure comprises a plurality of stacked current guiding sheets and an anti-corrosion layer sandwiched between two adjacent current guiding sheets.
Regarding claim 16, the primary reason for allowance is due to a computing node, wherein the mainboard comprises a first mainboard and a second mainboard, the second mainboard is located on a side of the first mainboard, and a first surface of the first mainboard and a first surface of the second mainboard face a same direction; the current guiding structure comprises a first current guiding strip and a first connection strip, and the first current guiding strip is disposed on a side of the first mainboard, and is fixedly connected to a through-current hole on the first mainboard; and one end of the first connection strip is fixedly connected to the first current guiding strip, and the other end of the first connection strip is connected to a through-current hole on the second mainboard.
Regarding claim 17, the primary reason for allowance is due to a computing node, wherein the mainboard comprises a third mainboard and a fourth mainboard; the third mainboard is disposed adjacent to the fourth mainboard, and a first surface of the third mainboard and a first surface of the fourth mainboard separately face two opposite sides; and the current guiding structure is sandwiched between the third mainboard and the fourth mainboard, and is separately fixedly connected to a through-current hole on the third mainboard and a through-current hole on the fourth mainboard.
Regarding claim 19, the primary reason for allowance is due to a computing node, wherein the computing node further comprises a current convergence apparatus; and the current convergence apparatus has a plurality of electric energy input parts and an electric energy output part, each electric energy input parts is connected to the power supply, and the electric energy output part is connected to the current guiding structure.
Conclusion
The FOLLOWING PRIOR ART is made of record and not relied upon, but considered pertinent to applicant's independent claims 1 and 20:
Zhang (CN112055499A) (Shencloud-Mitac), can be used to map the limitation structures in Independent Claims 1 and 20 in a 35 U.S.C. 102 or 103 rejection
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
