Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma et al. PG Pub US 2008/0320214 A1 [hereinafter Ma].
Regarding claim 1, Ma discloses:
receiving a plurality of read commands respectively at a set of media controllers coupled to a set of memory interfaces (Host system or PC motherboard 902 sends commands, addresses, and data over an interface bus to I/O interface circuit 904 on flash system 910 [0051] this command packet contains a flash-read command and an address to begin reading from and a length to read, so NVM controller 76 instructs flash memory blocks 68 to begin reading the requested data [100]); and
preventing the set of media controllers from executing the plurality of read commands responsive to determining that at least one of the set of memory interfaces is currently busy (FIG. 18 is a flowchart of busy handling for multiple interleaved channels of flash. When multiple channels of single-chip flash-memory devices 73 are interleaved, such as shown in FIG. 16, all single-chip flash-memory devices within an interleave share command and data buses, step 780. Only one single-chip flash-memory device 73 in each interleave can receive a command at a time over the shared command buses [0136] Busy1 is asserted to smart storage switch 30 by single-chip flash-memory device 73 after a command is received, step 782. Busy1 in step 782 is generated by the first single-chip flash-memory device 73 while busy2 in step 786 is generated by the second single-chip flash-memory device 73. Busy1 and Busy2 are connected together as the shared busy line [0137]).
Regarding claim 2 the limitations of this claim have been noted in the rejection of claim 1. Ma also discloses:
further comprising allowing the set of media controllers to execute the plurality of read commands responsive to determining that the set of memory interfaces are no longer busy (The smart storage switch monitors the ready lines from each single-chip flash-memory devices 73, step 788. When none of the busy lines are asserted, step 790, then the commands have been completed [0139]).
Regarding claim 3 the limitations of this claim have been noted in the rejection of claim 1. Ma also discloses:
further comprising substantially simultaneously executing the plurality of read commands via the set of media controllers (Since two single-chip flash-memory devices 73 have separate command and data buses for their own dedicated use, both single-chip flash-memory devices 73 may be accessed at the same time. In FIG. 19A, chip enables CE to both single-chip flash-memory devices are asserted low to begin access cycles, and separate commands CMD1, CMD2 are latched in using command-latch-enable CLE lines and separate addresses DEV2 LBA and DEV1 LBA are latched in using separate address-latch-enable ALE signals. Write data from the host and buffered by smart storage switch 30 (DEV2, DEV1 on DQ data buses) is latched into the single-chip flash-memory devices using data strobes DQS2, 1. These two accesses occur simultaneously during time period 90 [0143]).
Regarding claim 4 the limitations of this claim have been noted in the rejection of claim 1. Ma also discloses:
further comprising preventing the set of media controllers from executing the plurality of read commands by preventing the set of media controllers from accessing memory devices coupled to the set of media controllers via the set of memory interfaces (FIG. 18 is a flowchart of busy handling for multiple interleaved channels of flash. When multiple channels of single-chip flash-memory devices 73 are interleaved, such as shown in FIG. 16, all single-chip flash-memory devices within an interleave share command and data buses, step 780. Only one single-chip flash-memory device 73 in each interleave can receive a command at a time over the shared command buses [0136] Busy1 is asserted to smart storage switch 30 by single-chip flash-memory device 73 after a command is received, step 782. Busy1 in step 782 is generated by the first single-chip flash-memory device 73 while busy2 in step 786 is generated by the second single-chip flash-memory device 73. Busy1 and Busy2 are connected together as the shared busy line [0137]).
Allowable Subject Matter
Claims 5-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 5-20 contain the same subject matter that rendered parent patent US 12,164,773 allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kang PG Pub US 2009/0207663 A1 discloses a NAND gate that receives an output signal from the inverter and an internal ready/busy signal generated in the flash memory internal circuit.
Agarwal et al. PG Pub US 2019/0042500 A1 discloses a DIMM which includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN D ROSSITER whose telephone number is (571)270-3788. The examiner can normally be reached M-F 8AM-4PM.
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/SEAN D ROSSITER/ Primary Examiner, Art Unit 2133