Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 9 and 15.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 11/21/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 11/21/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US 12,266,414 B2; “Park et al”).
Regarding to independent claim 1, Part et al in Figures 1-14 are directly discloses a memory device (a system 10 include a memory device 200, Fig. 1) comprising:
a memory block (a memory cell array 210, Figs. 1-2) including a plurality of memory cells (the memory cell array 210 including a plurality of memory cells) connected to a plurality of word lines (the memory cell array 210 including a plurality of memory cells, each of the memory cells coupled to the plurality of word line; Fig. 1, column 3, lines 4-6), respectively;
a peripheral circuit (a peripheral circuit 220, Figs. 1-2) configured to perform a test program operation (a test logic circuit 230, Figs. 1-2) and a pass bit detection operation of measuring a program speed of memory cells (the memory cell array 210) connected to a selected word line among the plurality of word lines during a test o operation (for example, the peripheral circuit 220 may include various types of circuit such as test logic circuit 230 that perform various functions related to a test operation in a test mode of the memory cell array 210, Figs. 1-2); and
control logic (a memory controller 100 include a test controller circuit 110, Figs. 1-2) configured to control the peripheral circuit (the peripheral circuit 220) to perform the test operation (the test logic circuit 230), and set a potential of a pass voltage (a supply voltage VDD/VPP, V_T, Figs. 1-2) to be used in a program operation, or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed (for example, the memory controller 100 may provide various signals to the memory device 200 through a memory interface to control memory operation and a voltage obtained by regulating the supply voltage VDD/VPP to the cell array 210 during the operation, see at least in Figs. 1-2, column 3, lines 1 to column 6, lines 57 and the related disclosures).
Allowable Subject Matter
6. Claims 2-8, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, the control logic comprises: a test operation controller configured to control the peripheral circuit to perform the test operation; and an operating voltage setting circuit configured to, when a number of memory cells having threshold voltages equal to or higher than a set threshold voltage value is equal to or greater than a set number as a result of the pass bit detection operation, set the potential of the pass voltage or the time point at which the pass voltage is to be applied, based on the number of times the test program operation is performed.
With respected to dependent claims 3-5, the prior art fails to tech or suggest the claimed limitations, namely, the peripheral circuit is configured to: apply the program voltage to the selected word line during the test program operation, and re-perform the test program operation when a number of pass bits corresponding to the number of memory cells programmed to have threshold voltages equal to or higher than the set threshold voltage value is less than a set number during the pass bit detection operation.
With respected to dependent claims 6-8, the prior art fails to tech or suggest the claimed limitations, namely, the peripheral circuit comprises: a voltage generator configured to generate operating voltages including a program voltage, a first pass voltage, a second pass voltage, a set read voltage, and a read pass voltage to be applied to the plurality of word lines; an address decoder configured to transfer the operating voltages to the plurality of word lines; and a page buffer group configured to apply a program-enable voltage to bit lines of the memory block during the test program operation, and detect memory cells programmed to have threshold voltages equal to or higher than a set threshold voltage among the memory cells connected to the selected word line through the bit lines during the pass bit detection operation.
7. Claims 9-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 9: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “detecting a number of pass bits corresponding to memory cells having threshold voltages equal to or higher than a set threshold voltage among memory cells connected to the selected word line by performing a pass bit detection operation; wherein when the number of pass bits is less than a set value, re-performing the test program operation using a new program voltage; and wherein when the number of pass bits is equal to or greater than the set value, setting a level of a pass voltage to be used in a program operation or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.” in a method of operating a memory device as claimed in the independent claim 9. Claims 10-14 are also allowed because of their dependency on claim 9; or
Per claim 15: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “detecting a number of pass bits corresponding to memory cells having threshold voltages equal to or higher than a set threshold voltage among memory cells connected to the selected word line by performing a pass bit detection operation; wherein when the number of pass bits is less than a set value, resetting a potential of a pass voltage to be applied to word lines adjacent to the selected word line or a time point at which the pass voltage is to be applied, and re-performing the test program operation; and wherein when the number of pass bits is equal to or greater than the set value, setting a level of a pass voltage to be used in a program operation or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.” in a method of operating a memory device as claimed in the independent claim 15. Claims 16-20 are also allowed because of their dependency on claim 15.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US. 12,580,034 B2) discloses memory device and method of fabricating memory device including a test circuit.
Park (US. 12,190,973 B2) discloses memory device performing sensing operation and method of operating the same.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights