DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 27 February, 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed 8 December, 2025. Examiner further acknowledges amendments to the claims which have been rejected upon further search and consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Esaka et al (U.S. Patent Pub. No. 2021/0223962), hereinafter referred to as Esaka.
As for claim 1, Esaka teaches an apparatus, comprising: a controller associated with a memory device (Fig. 2 controller 4 attached to DRAM 6 and NAND 5), wherein the controller is configured to cause the apparatus to: receive a plurality of write commands to write data to a non-volatile memory device; monitor parameters associated with the plurality of write commands received; select to store data associated with the plurality of write commands using a first type of block of the non-volatile memory device based at least in part on monitoring the parameters, the first type of block selected from a plurality of types of blocks including the first type of block and a second type of block, wherein the plurality of types of blocks correspond to different data storage densities; (¶ 0191 write requests are received and monitored until reaching a size, after which they are transferred to a buffer 161 in DRAM 6 to be stored in the NVM for storage in a QLC block; ¶ 0173 a plurality of QLC blocks are allocated and a plurality of SLC blocks are allocated); and transfer the data associated with the plurality of write commands from a write buffer of a volatile memory device to the first type of block of the non-volatile memory device based at least in part on selecting to store the data associated with the plurality of write commands using the first type of block. (¶ 0194, lines 7-17 disclose writing data from the internal buffer in DRAM to QLC blocks based on QLC block size), achieving the claimed limitation.
As for claim 2, the previously cited references teach the apparatus of claim 1. Additionally, Esaka teaches that the controller is further configured to cause the apparatus to: transition from writing the data to the first type of block to writing the data to a second type of block of the non-volatile memory device based at least in part on monitoring the parameters associated with the plurality of write commands. Esaka ¶ 0103 discloses inactivate commands which trigger a change in write behavior. ¶ 104, lines 6-10 disclose writing remaining data to the shared flash buffer instead of the first storage region in response to the inactivate indication. As shown in Fig. 5, the buffer may be constituted of SLC blocks and the region may be constituted of QLC blocks, achieving the claimed limitation of writing to a different block type based on parameters associated with the write commands.
As for claim 3, the previously cited references teach the apparatus of claim 1. Additionally, Esaka teaches that the controller is further configured to cause the apparatus to: transition from writing the data to a second type of block to writing the data to the first type of block of the non-volatile memory device based at least in part on monitoring the parameters associated with the plurality of write commands. Esaka ¶ 0148 discloses that a write request directed to a previously closed QLC block results in the data being written to it from the shared flash buffer (i.e. data is written to QLC instead of SLC). This may occur directly after inactivating the block (which results in writing to SLC; ¶ 0145-0146), achieving the claimed limitation.
As for claim 4, the previously cited references teach the apparatus of claim 1. Additionally, Esaka ¶ 0194, lines 7-17 disclose transferring write data from a host buffer to an internal write buffer before writing data from the internal buffer in DRAM to QLC blocks, achieving the claimed limitation.
As for claim 5, the previously cited references teach the apparatus of claim 1. Additionally, the "first type" of block referenced in the rejection is a QLC block (also a form of multi-level cell block; ¶ 0194, lines 7-17 disclose writing data from the internal buffer in DRAM to QLC blocks). The "second type" as addressed in the rejection of claim 2 are SLC blocks, as shown in Fig. 5 wherein the buffer may be constituted of SLC blocks and the region may be constituted of QLC blocks, achieving the claimed limitation.
As for claim 6, the previously cited references teach the apparatus of claim 1. Additionally, because the invention disclosed by Esaka may alternate between writing to first and second type blocks in much the same manner (¶ 0103 discloses inactivate commands which trigger a change in write behavior. ¶ 104, lines 6-10 disclose writing remaining data to the shared flash buffer instead of the first storage region in response to the inactivate indication; ¶ 0148 discloses that a write request directed to a previously closed QLC block results in the data being written to it from the shared flash buffer), the first and second types set forth in the rejection of claim 5 are interchangeable, achieving the claimed limitation.
As for claim 17, Applicant is directed to the rejection of claim 1, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 18, Applicant is directed to the rejection of claim 2, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 19, Applicant is directed to the rejection of claim 3, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 20, Applicant is directed to the rejection of claim 1, as the claims include the same limitations and are therefore rejected on the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Esaka in view of Lewis et al (U.S. Patent No. 9,436,391), hereinafter referred to as Lewis.
As for claim 7, the previously cited references teach the apparatus of claim 1. Esaka does not teach determining a throughput of the data associated with the plurality of write commands over a time interval, wherein selecting to store the data associated with the plurality of write commands is based at least in part on the throughput of the data associated with the plurality of write commands over the time interval satisfying a threshold. However, Lewis Column 8, lines 22-33 disclose determining whether the throughput of I/O requests (including write requests, Column 3, lines 7-8) exceeds a threshold rate over a specified time interval, and lines 36-39 disclose selecting a storage volume based on the determination. If combined with the disclosure of Esaka, selecting to store data would be based on determining a throughput of the analyzed write requests. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Lewis in order to store data according to throughput and benefit from efficient and scalable I/O scheduling (Title) and address the issues of servicing a large number of client I/O requests (Column 1, lines 10-28).
As for claim 9, the previously cited references teach the apparatus of claim 7. Additionally, Lewis Column 8, lines 55-64 disclose determining whether the throughput of I/O requests (including write requests, Column 3, lines 7-8) meets a second threshold rate over a specified time interval, and lines 64-67 disclose selecting a storage volume based on the determination according to a request queue depth or a set priority, a process explained in Column 9, lines 1-24. A person of ordinary skill could configure the apparatus of Esaka to select either the disclosed SLC buffer (volume 1) or the QLC region (volume 2) and perform normal write processes which include transitioning between block types (as cited in the rejections of claims 2 and 3) based at least in part on the write throughput if utilizing the disclosure of Lewis. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Lewis in order to store data according to throughput and benefit from efficient and scalable I/O scheduling (Title) and address the issues of servicing a large number of client I/O requests (Column 1, lines 10-28).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Esaka in view of Lewis and Cochran et al (U.S. Patent Pub. No. 2005/0097290), hereinafter referred to as Cochran. The previously cited references teach the apparatus of claim 7. They do not teach the remaining limitations of claim 8. However, Cochran teaches a write block size switching method for optimizing throughput, and ¶ 0036 discloses that throughput is dependent on write block size (i.e. transfer size of write commands), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Cochran in order to effectively respond to changes in a communication link (¶ 0035) and alleviate the effects of inflexible block sizes on copy operations (¶ 0036 discloses prior art issues, ¶ 0037 discloses the embodiment for write block size manipulation).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Esaka in view of Freilich (U.S. Patent No. 10,198,205).
As for claim 10, the previously cited references teach the apparatus of claim 1. They do not teach the remaining limitations of claim 10. However, Freilich teaches an embodiment including determining a size of the write buffer used to store the data associated with the plurality of write commands, wherein selecting to store the data associated with the plurality of write commands is based at least in part on the size of the write buffer used to store the data satisfying a threshold (Column 26, lines 50-61 disclose a method including determining a capacity of a write buffer exceeds a threshold and queueing write operations (i.e. selecting to store data) as a result), achieving the claimed limitation. A person of ordinary skill in the art could combine this teaching with the write buffers disclosed by Esaka in order to select to store data based at least in part on the size of the write buffer used to store the data satisfying a threshold. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Freilich to benefit from disclosed techniques related to write buffers, which improve write latency and efficiency (Column 6, lines 11-37).
As for claim 12, the previously cited references teach the apparatus of claim 10. Additionally, a person of ordinary skill could configure the apparatus of Esaka to perform normal write processes which include transitioning between block types (as cited in the rejections of claims 2 and 3) based at least in part on the write buffer size satisfying a threshold if utilizing the disclosure of Freilich as cited in the rejection of claim 10, as Freilich's disclosure simply results in writes being queued to storage devices (Column 26, lines 50-61).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Esaka in view of Bueb (U.S. Patent Pub. No. 2022/0057952).
As for claim 13, the previously cited references teach the apparatus of claim 1. They do not explicitly teach the remaining limitations of claim 13. However, Bueb teaches migrating (i.e. selecting to write) data based on determining whether a system is idle, which includes determining that its command queue is empty (e.g. no write commands in the queue, which would mean no data in the write buffer; ¶ 0047, lines 1-7), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Bueb in order to benefit from methods for managing the temperature of storage devices (¶ 0046).
As for claim 15, the previously cited references teach the apparatus of claim 13. Additionally, Esaka teaches determining whether an amount of data in the write buffer satisfies a threshold, wherein selecting to store the data in the first type of block based at least in part on determining whether the amount of data in the write buffer satisfies the threshold (¶0123 discloses writing data when the data in the write buffer is of a predefined write size), achieving the claimed limitation.
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Esaka in view of Freilich and Bueb.
As for claim 11, the previously cited references teach the apparatus of claim 10. Additionally, Freilich Column 26, lines 50-61 disclose a method including determining a capacity of a write buffer exceeds a threshold and queueing write operations (i.e. selecting to store data) as a result They do not explicitly teach the remaining limitations of claim 11. However, Bueb teaches processing logic which can set second threshold capacity values for migration greater than a first threshold value (¶ 0048). If combined with the disclosure of Freilich, a person of ordinary skill could dynamically set a second greater threshold value for queuing writes, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Bueb in order to benefit from methods for reducing latency caused by interrupting commands during a data migration (e.g. data write) (¶ 0048, lines 1-7).
As for claim 14, the previously cited references teach the apparatus of claim 13. They do not explicitly teach the remaining limitations of claim 14. However, Freilich teaches an embodiment including determining whether the command queue satisfies a threshold, wherein selecting to store the data in the first type of block based at least in part on determining whether the command queue satisfies the threshold (Freilich Fig. 10 step 906 item 1002 includes shows determining write queue depth satisfies threshold, step 912 includes increasing devices servicing writes which would result in data being selected for writing), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Freilich to benefit from disclosed techniques related to write buffers, which improve write latency and efficiency (Column 6, lines 11-37).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Esaka in view of Soberanes et al (U.S. Patent Pub. No. 2022/0147270), hereinafter referred to as Soberanes. The previously cited references teach the apparatus of claim 1. They do not teach the remaining limitations of claim 16. However, Soberanes teaches a write booster access mode (¶ 0044 discloses the write booster mode).A person of ordinary skill in the art could combine the teaching of Soberanes with the disclosure of Esaka wherein write parameters are monitored to be written to the device, including in an SLC write mode (¶ 0191 write requests are received and monitored until reaching a size, after which they are transferred to a buffer 161 in DRAM 6 to be stored in the NVM; ¶ 104, lines 6-10 disclose writing remaining data to the shared flash buffer instead of the first storage region in response to an inactivate indication. As shown in Fig. 5, the buffer may be constituted of SLC blocks) very similar to the disclosed write boost mode. This would result in the monitoring and writing process of Esaka taking place after initiating a write boost, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Soberanes in order to selectively employ the disclosure of Esaka and benefit from increased efficiency and lifespan of a memory system (¶ 0012, lines 21-30).
Response to Arguments
Applicant's arguments (see page 7 of response filed 27 February, 2026) have been fully considered but they are not persuasive. Esaka was found to teach the added limitations, as shown in the updated rejection of claim 1. As written, the claims do not require a selection between two types of blocks, simply a selection to store data in a given block type based on a monitored parameter. Accordingly, Esaka ¶ 0194 (cited in rejection; addresses transferring data to non-volatile memory) discloses that data may be selected to be stored in a QLC block in non-volatile memory when it reaches a specified size, achieving the claimed limitation. Additionally and in the interest of informing further amendments, Esaka ¶ 0160-0161 disclose a process of writing specifically to SLC blocks in an SLC mode instead of QLC blocks in a normal mode (i.e. selecting to write to SLC instead of QLC), which is elaborated upon further in the disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZAKARIA MOHAMMED BELKHAYAT/ Examiner, Art Unit 2139
/REGINALD G BRAGDON/ Supervisory Patent Examiner, Art Unit 2139
Prosecution Insights