DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5, 7, 9, 11-15 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5, 7, 8, 11-14, 18 and 20 respectively of U.S. Patent No. 12190432 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because they a broad obvious variation of U.S. Patent No. 12190432 B2.
Current Application
US Patent 12190432 B2
1. A graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the graphics processing system comprising: a plurality of first hardware elements, each configured to calculate a respective first output based on coordinates for a pixel; a plurality of second hardware elements, each configured to calculate a respective second output based on coordinates for a subsample within the pixel; and hardware logic configured to generate an edge test output value or depth calculation value based on at least one of the second outputs; wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.
1. A graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the graphics processing system comprising: a first hardware element, configured to calculate a respective first output based on coordinates for a microtile within a tile; a plurality of second hardware elements, each configured to calculate a respective second output based on coordinates for a subsample within a pixel; and hardware logic configured to generate an edge test output value or depth calculation value based on at least one of the second outputs, wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.
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15. A method of calculating an edge test output value or a depth calculation value in a graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the method comprising: in each of a plurality of first hardware elements, calculating a first output based on coordinates of a pixel; in each of a plurality of second hardware elements, calculating a respective second output based on coordinates for a subsample within the pixel; and generating an edge test output value or a depth calculation value based on at least one of the second outputs.
18. A method of calculating an edge test output value or a depth calculation value in a graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the method comprising: in a first hardware element, calculating a first output based on coordinates of a microtile; in each of a plurality of second hardware elements, calculating a respective second output based on coordinates for a subsample within a pixel; and generating an edge test output value or a depth calculation value based on at least one of the second outputs.
19. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the graphics processing system comprising: a plurality of first hardware elements, each configured to calculate respective first output based on coordinates for a pixel; a plurality of second hardware elements, each configured to calculate a respective second output based on coordinates for a subsample within the pixel; and hardware logic configured to generate an edge test output value or depth calculation value based on at least one of the second outputs; wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.
20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the graphics processing system comprising: a first hardware element, configured to calculate respective first output based on coordinates for a microtile within a tile; a plurality of second hardware elements, each configured to calculate a respective second output based on coordinates for a subsample within a pixel; and hardware logic configured to generate an edge test output value or depth calculation value based on at least one of the second outputs, wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.
Allowable Subject Matter
Claims 1-3, 5, 7, 9, 11-15 and 19 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: No prior art teaches the italicized and bolded featuresClaim 1. A graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the graphics processing system comprising: a plurality of first hardware elements, each configured to calculate a respective first output based on coordinates for a pixel; a plurality of second hardware elements, each configured to calculate a respective second output based on coordinates for a subsample within the pixel; and hardware logic configured to generate an edge test output value or depth calculation value based on at least one of the second outputs; wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.Claims 2-14 depend on allowable claim 1.Claim 15. A method of calculating an edge test output value or a depth calculation value in a graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the method comprising: in each of a plurality of first hardware elements, calculating a first output based on coordinates of a pixel; in each of a plurality of second hardware elements, calculating a respective second output based on coordinates for a subsample within the pixel; and generating an edge test output value or a depth calculation value based on at least one of the second outputs.Claims 16-18 depend on allowable claim 15.Claim 19. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing system arranged to render a scene in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, and each tile is sub-divided into a plurality of microtiles, each microtile comprising at least one pixel, the at least one pixel comprising one or more subsamples, the graphics processing system comprising: a plurality of first hardware elements, each configured to calculate respective first output based on coordinates for a pixel; a plurality of second hardware elements, each configured to calculate a respective second output based on coordinates for a subsample within the pixel; and hardware logic configured to generate an edge test output value or depth calculation value based on at least one of the second outputs; wherein the scene is rendered in said rendering space using the generated edge test output values or depth calculation values.Relevant prior arts:US 20180197271 A1 A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. The graphics processing unit also comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles. The graphics processing unit also comprises scheduling logic configured to schedule, in dependence upon the cost indications, the sets of one or more tiles for processing on the one or more processing cores.
Conclusion
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/MARTIN MUSHAMBO/ Primary Examiner, Art Unit 2615 5/30/2026
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