DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 03/09/2026. Claims 1,2, 8, 9, 15 and 16 have been amended. Claims 3-4, 10-11, and 17-18 have been cancelled. Claims 21-23 have been added. Claims 1-2, 5-9, 12-16, and 19-23 are pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.CN202210575022.5 filed on 05/24/2022 and No.CN202211016161.0, filed on 08/24/2022.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the examiner’s response set forth below.
(1)In view of the amendments, rejections of claim 4, 11, and 18, under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, have been withdrawn.
(2) Applicant contends that, regarding claim 1, Shifer does not teach or suggest the recited limitation “identifying a second address based on an address of a data block in which the first address is located and an address mapping relationship, wherein the second address indicates a location, in the controller, at which access frequency of accessing the data block is stored, and the address mapping relationship indicates a mapping relationship between the address of the data block and an address of storage space in which the access frequency is stored;” Specifically, Applicant argues “[a]pplicant respectfully submits that Shifer refers to identifying hot data in far memory through hot bit making. In contrast to the features of claim 1 as presently amended, Shifer does not teach or suggest identifying a second address based on both an address of a data block in which the first address is located and an address mapping relationship, and much less (1) that the second address indicates a location, in the controller, at which access frequency of accessing the data block is stored, and (2) that the address mapping relationship indicates a mapping relationship between the address of the data block and an address of storage space in which the access frequency is stored.” The Examiner respectfully disagrees.
Shifer discloses an address cache 205 configured to map a far memory address (i.e. first address based on an access request) to a far memory (FM) cache address ([0016], [0036]). The address cache 205 includes a first level cache 206 which is located within a controller ([0018], Fig.2). Each cache slot in cache 206 includes meta data associated with cached address, including access frequency information, such as a hot bit ([0028], [0029]), a bit vector 301, and cache line counter 302 ([0047]). The bit vector 301 and cache line counter 302 track access frequency information for a page in the FM cache 203 corresponding to the requested data in far memory 202 ([0049]). Accordingly, when a far memory address is accessed, Shifer identifies a corresponding cache line (i.e., a data block) in FM cache 203, and further identifies a cache slot in cache 206 that stores metadata - including access frequency information – for that data block. Thus, the identified cache slot in cache 206 corresponds to “a second address based on an address of a data block in which the first address is located, wherein the second address indicates a location, in the controller, at which access frequency of accessing the data block is stored”, as recited in claim 1.
Furthermore, Shifer’s mapping from far memory address (and corresponding FM cache address) to cache slots in cache 206 constitutes the claimed address mapping relationship. Specifically, this mapping defines a relationship between (i) the address of the data block (e.g. a page or cache line corresponding to the requested far memory address), and (ii) an address of storage space (i.e., the cache slot location in cache 206) in which access frequency information is stored. Therefore, the mapping performed by address cache 205 satisfies the claimed requirements of an address mapping relationship between a data block address and a storage location for access frequency.
Shifer further discloses that address cache 206 is implemented as set associative caches having multiple sets, each having a plurality of cache slots into which pages or address mappings may be inserted ([0019]). This set-and-slot structure defines discrete and uniquely identifiable storage locations within the controller. As would be understood by a person of ordinary skill in the art, each cache slot corresponds to a specific, identifiable location (i.e., and addressable location) within the cache structure. While Shifer may not explicitly label a cache slot as an “address”, it would have been obvious for person of ordinary skill in the art to treat each cache slot as having a corresponding address or location identifier, since cache structures inherently rely on indexing (e.g., set index and way) to identify the specific storage locations. Therefore, identifying a cache slot storing access frequency information corresponds to identifying the claimed “second address”, as such identification would have been an obvious implementation detail in view of well-known cache addressing techniques.
(3) Th rest of Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(4) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 7-9, 12, 14-16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shifer et al. (US 2020/0226066), hereinafter Shifer in view of Liu et al. (US2021/0342094), hereinafter Liu.
Regarding claims 1, 8, and 15, taking claim 15 as exemplary, Shifer teaches a computer device (Shifer, [0063], computing system 500 (e.g., a smartphone, a tablet computer, a laptop computer, a desktop computer, a server computer, etc.)), wherein the computer device comprises at least one processor (Shifer, [0063], the basic computing system 500 may include a central processing unit 501) and a memory, and the memory comprises a storage device and a controller (Shifer, [0018], The first level is a smaller cache that resides on the same semiconductor chip as the memory controller 204. The second level 207 is a larger cache that is implemented with a reserved portion of the DRAM; [0063], the basic computing system 500 may include … and the main memory controller 517; [0071]), and the controller comprises a storage circuit and a processing circuit, and the storage circuit stores computer instructions for execution by the processing circuit to (Shifer, [0065], The main memory controller 517 can include logic circuitry to perform any of the functions described at length above):
determine a first address based on an access request, wherein the access request indicates an operation performed on a memory of a computer device by an application program run by the at least one processor (Shifer, [0064], The general-purpose processing cores 515 typically execute the system and application software of the computing system) in the computer device (Shifer, [0063], computing system 500) in which the controller is located, and the first address is a physical address in the memory (Shifer, [0014]; [0015], upon the main memory controller's reception of a request whose target address maps to a page in far memory 202; [0016]; [0048]);
identify a second address based on an address of a data block (Shifer, [0015], a page in far memory 202) in which the first address is located and an address mapping relationship (Shifer, [0066], the address cache 205 keeps mappings of a far memory page address to a FM cache page address), wherein the second address indicates a location, in the controller, at which access frequency of accessing the data block is stored (Shifer, [0018], the address cache 205 includes two levels 206, 207; [0038], the address cache 205 includes two levels: 1) a first level 206 that is on the same chip as the memory controller 204), and the address mapping relationship indicates a mapping relationship between the address of the data block and an address of storage space in which the access frequency is stored (Shifer, [0028], the meta data of each cache slot is therefore extended to include a “hot bit”; [0047], the additional meta data includes a bit vector 301 and a “cache line” counter 302; [0049], Over time the page may get a number of accesses while the page's address sits in the address cache 205 (whether in the first or second levels 206, 207) … Upon a first instance of an access whose targeted cache line corresponds to a bit in the bit vector 301, the value of the bit is flipped from a 0 to a 1 and the cache line counter 302 is incremented; Note – the identified cache slot in cache 206 corresponds to “a second address”.);
collect statistics about the access frequency of accessing the data block stored at the first address (Shifer, In order for the migration to actually happen, however, the memory controller 204 needs to have a mechanism for identifying pages that demonstrate some indicia of being regularly accessed over extended periods of time; [0028], the meta data of each cache slot is therefore extended to include a “hot bit” along with the MRU bit; [0030], After a page's hot bit is asserted, if the page subsequently receives another hit while in the FM cache 203, the memory controller 204 takes affirmative action to notify system software of the existence of the hot page), wherein a size of the data block is a multiple of unit storage space in the memory that is accessible to the at least one processor (Shifer, [0047], where the page has 64 cache lines); and
determine an access popularity of the data block based on the access frequency (Shifer, [0041], Hot pages are identified by tracking, for each address in the address cache 205, the number of “round trips” an address has taken thrashing between the first and second caching levels 206, 207; [0050]; [0052]).
Shifer teaches a main memory controller includes a logic circuity performing functions, nevertheless, Shifer does not explicitly teach the controller comprises a storage circuit and a processing circuit, and the storage circuit stores computer instructions for execution by the processing circuit, as claimed.
However, Shifer in view of Liu teaches controller comprises a storage circuit and a processing circuit, and the storage circuit stores computer instructions for execution by the processing circuit (Liu, [0020], where the memory controller comprises one or more processors; and one or more machine-readable media storing instructions that, when executed, cause the one or more processors to perform the above-described operations).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shifer to incorporate teachings of Liu to include a processing unit and a memory storing instructions for the processing unit in a memory controller. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shifer with Liu because it improves performance and flexibility of the storage system disclosed in Shifer by allowing a memory controller to have its own processor.
Claims 1 and 8 have similar limitations as claim 15 and they are rejected for the similar reasons.
Regarding claims 2, 9, and 16, taking claim 16 as exemplary, the combination of Shifer teaches all the features with respect to claim 15 as outlined above. The combination of Shifer further teaches the computer device according to claim 15, wherein the collecting statistics about the access frequency of accessing the data block stored at the first address comprises: collecting statistics about the access frequency of accessing the data block stored at the unit storage space to which the first address belongs is located (Shifer, [0032]; [0048], the address of a memory request that is received by the memory controller 204 targets a specific cache line within a page. As such, the address identifies not only the target page but also the target cache line; [0047], the slots in the address cache 205 are further enhanced to include meta data that tracks, to some extent, specific cache line accesses in their respective pages … The bit vector 301 is a vector where each bit element of the vector corresponds to a specific cache line in the page that the slot entry corresponds to. For example, according to one embodiment, the bit vector 301 is an eight bit vector where the first bit corresponds to the 8th cache line in the page, the second bit corresponds to the 16th cache line in the page, . . . , and the eighth bit corresponds to the 64th cache line in the page (where the page has 64 cache lines; [0053]).
Claims 2 and 9 have similar limitations as claim 16 and they are rejected for the similar reasons.
Regarding claims 5, 12, and 19, taking claim 19 as exemplary, the combination of Shifer teaches all the features with respect to claim 15 as outlined above. The combination of Shifer further teaches the computer device according to claim 15, wherein the size of the data block is a size of one page in the memory that is accessible to the at least one processor (Shifer, [0015], upon the main memory controller's reception of a request whose target address maps to a page in far memory 202; [0030], the response message to the requesting CPU core that (which includes read data in the case of a read request); Note -indicating read/write requests are issued by CPU cores.).
Claims 5 and 12 have similar limitations as claim 19 and they are rejected for the similar reasons.
Regarding claims 7 and 14, taking claim 7 as exemplary, the combination of Shifer teaches all the features with respect to claim 1 as outlined above. The combination of Shifer further teaches the method according to claim 1, wherein a size of the unit storage space is a size of a cache line when the at least one processor accesses the memory (Shifer, [0048], the address of a memory request that is received by the memory controller 204 targets a specific cache line within a page; [0030], the response message to the requesting CPU core that (which includes read data in the case of a read request); Note -indicating read/write requests are issued by CPU cores.).
Claim 14 has similar limitations as claim 7 and is rejected for the similar reasons.
Claim(s) 6, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shifer and Liu as applied to claims 1, 8, and 15 respectively above, and further in view of Luiz Ramos et al. (Page Placement in Hybrid Memory Systems; ICS’11: Proceedings of the international conference on Supercomputing, Pages 85 – 95; published 31 May 2011), hereinafter Luiz Ramos.
Regarding claims 6, 13, and 20, taking claim 20 as exemplary, the combination of Shifer teaches all the features with respect to claim 15 as outlined above. The combination of Shifer does not explicitly teach the computer device according to claim 15, wherein the size of the data block is a size of an interleaved data block in the memory that is accessible to the at least one processor in an interleaving manner, and the interleaving manner comprises that the at least one processor in the computer device distributes, to a plurality of memories for an operation, data of the operation performed by the application program on the memory of the computer device, as claimed.
However, the combination of Shifer in view of Ramos teaches the computer device according to claim 15, wherein the size of the data block is a size of an interleaved data block in the memory that is accessible to the at least one processor in an interleaving manner, and the interleaving manner comprises that the at least one processor in the computer device distributes, to a plurality of memories for an operation, data of the operation performed by the application program on the memory of the computer device (Ramos, page 85, right column - The policy efficiently ranks pages according to popularity (access frequency) and write intensity, migrating top-ranked pages to DRAM; page 91, left column - The MC implements cache block-level bank interleaving and page-level channel interleaving.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Shifer to incorporate teachings of Ramos to implement cache page-level channel interleaving for distributing data. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shifer with Ramos because it improves performance of the storage system disclosed in the combination of Shifer by enabling parallel memory processing.
Claim(s) 21, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shifer and Liu as applied to claims 1, 8, and 15 respectively above, and further in view of Roberts et al. (US2023/0058668), hereinafter Roberts.
Regarding claims 21, 22, and 23, taking claim 23 as exemplary, the combination of Shifer teaches all the features with respect to claim 15 as outlined above. The combination of Shifer does not explicitly teach the computer device according to claim 15, wherein the collected statistics indicate a number of access times, as claimed.
However, the combination of Shifer in view of Roberts teaches the computer device according to claim 15, wherein the collected statistics indicate a number of access times (Roberts, [0061], the cache line structure 300 further includes … an access counter 312 (F); [0065], The access counter 312 can include one or more bits set to indicate a recency or frequency at which the cache line is accessed … the counter can be incremented each time the host interval includes an access request for the particular cache line).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shifer to incorporate teachings of Roberts to include a field in each cache line that tracks number of access times. As such, data determined to be infrequently accessed can be compressed/encrypted in order to reduce storage space. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shifer with Roberts because it improves efficiency of the storage system disclosed in the combination of Shifer by compress/encrypt data that are determined to be infrequently accessed which reduces storage space.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Roberts (US 2023/0244598) teaches tracking access of cache lines within a page of memory ([0044]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
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/NANCI N WONG/ Primary Examiner, Art Unit 2137
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