DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 01/15/2024. It is noted, however, that applicant has not filed a certified copy of the CHINA 202410061180.8 application as required by 37 CFR 1.55.
Oath/Declaration
The Oath/Declaration filed on 11/21/2024 is hereby acknowledged.
Drawings
The drawings are objected to because some of the labeling are illegible in Fig. 3 and Fig. 10. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Paragraph [0056] recites “The first data rearrangement circuit 132”. However, earlier in paragraph [0054] and Fig. 4, discloses “The first data rearrangement circuit” labeled as 133. It is suggested to amendment paragraph [0056] as “The first data rearrangement circuit
Appropriate correction is required.
Claim Objections
Claims 1-5 are objected to because of the following informalities:
claim 1 recites the limitation “the data processing clock signal” in line 9-10 which appears to refer back to “the data processing clock signals” in line 3-4. It is suggested to amend the limitation “the data processing clock signal” in line 9-10 as “the data processing clock signals” in order to maintain consistent word usage and proper antecedent basis. Appropriate correction is required.
Claim 2 is objected to because of the following informalities: claim 2 recites the limitation “the data processing clock signal” in line 2-3 which appears to refer back to “the data processing clock signals” in line 3-4 in claim 1. It is suggested to amend the limitation “the data processing clock signal” in line 9-10 as “the data processing clock signals” in order to maintain consistent word usage and proper antecedent basis. Appropriate correction is required.
Claim 3 is objected to because of the following informalities: claim 3 recites the limitation “the M first serial and parallel conversion circuit” in line 3 which appears to refer back to “M first serial and parallel conversion circuits” in line 2. It is suggested to amend the limitation “the M first serial and parallel conversion circuit” in line 2 as “the M first serial and parallel conversion circuits” in order to maintain consistent word usage and proper antecedent basis. Appropriate correction is required.
Claim 4 is objected to because of the following informalities: claim 4 recites the limitation “The data processing clock signal” in line 4 which appears to refer back to “the data processing clock signals” in line 3-4 in claim 1 upon which claim 4 indirectly depends on. It is suggested to amend the limitation “the data processing clock signal” in line 4 as “the data processing clock signals” in order to maintain consistent word usage and proper antecedent basis. Appropriate correction is required.
Claim 5 is objected to because of the following informalities: claim 4 recites the limitation “third serial and parallel conversion circuit” in line 5 and 10 which appears to refer back to “third serial and parallel conversion circuits” in line 1-2. It is suggested to amend the limitation “third serial and parallel conversion circuit” in line 5 and 10 as “third serial and parallel conversion circuits”, respectively, in order to maintain in order to maintain consistent word usage and proper antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 recites the limitation “first data rearrangement circuits” in line 1-2. This requires more than one or plurality of “first data rearrangement circuit.” However the Specification (e.g. Fig. 4, Para. [0054]) state that there is only “the first data rearrangement circuit 133,” that is only one “first data rearrangement circuit 133.” Hence the disclosure does not provide support for multiple “the first data rearrangement circuits” as recited in claim 3.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the receiver" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the data transmitter" in line 5-6. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the transmission data" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "at least one bit of transmission data" in line 8-9. It is unclear if this “transmission data” is relating to “original transmission data” recited in line 5 or “the transmission data” recited in line 6 or is different from it.
Claim 1 recites the limitation "the parallel sample data" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "at least one data processing cycle" in line 10-11. It is unclear if this processing cycle is same or different from the “at least one data processing cycle” recited in line 9.
Claim 1 recites the limitation "the data selection circuit" in line 12. It is unclear if "the data selection circuit" is one of or different from “data selection circuits” recited in line 2.
Claim 1 recites the limitation "each data processing cycle" in line 12. It is unclear if this processing cycle is same or different from the “at least one data processing cycle” recited in line 9 and 10-11.
Claim 1 recites the limitation "the corresponding parallel sample data" in line 13. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "each data processing cycle" in line 13. It is unclear if this processing cycle is same or different from the “each data processing cycle” recited in line 12 or “at least one data processing cycle” recited in line 9 and 10-11.
Claim 2 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. The claim(s) must be in one sentence form only. Claim 2 is formulated using three sentences, where second sentence starts in line 7, and third sentence starts in line 9. It is suggested to amend theses line as “sub-clock signal, [[.]] and use the transmission data obtained by the interpolation process as the sampling data of the transmission data received in this data processing cycle in the ith first interpolation phase, and output it[[.]] where i is each integer value from 1 to M, including both 1 and M, and M is an integer greater than 1.”
Claim 2 recites the limitation "the first data processing sub-clock signal" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the ith output delay circuit" in line 4. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if the “the ith output delay circuit” is one of the “M output delay circuits” recited in line 1-2 or different from it.
Claim 2 recites the limitation “each data processing cycle” in line 4-5. It is unclear if this processing cycle is same or different from the “at least one data processing cycle” recited in line 9 and 10-11 in claim 1 upon which claim 2 depends on.
Claim 2 recites the limitation "the ith first interpolation phase" in line 5-6. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if the "the ith first interpolation phase" is one of the “M preset first interpolation phases” recited in line 2 or different from it.
Claim 2 recites the limitation "the interpolation process" in line 3. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if "the interpolation process" is same or different from “interpolation phase process” recited in line 5.
Claim 2 recites the limitation " the sampling data" in line 7-8. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "in this data processing cycle" in line 8. It is unclear what “this” data processing cycle is being referred to.
Claim 2 recites the limitation "and output it" in line 9. It is unclear what “it” is referring to “the transmission data” in line 5 or 7 or “sampling data” in line 7-8.
Claim 3 recites the limitation "M output delay circuits" in line 3. It is unclear if these "M output delay circuits" are same or different from “M output delay circuits” recited in line 1-2 in claim 2 upon which claim 3 depends on.
Claim 3 recites the limitation "the ith first serial and parallel conversion circuit" in line 5. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if the "the ith first serial and parallel conversion circuit " is one of the “M first serial and parallel conversion circuits” recited in line 2 or different from it.
Claim 3 recites the limitation "the first preset number of bits" in line 5-6. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the serial sample data" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the multiple-bit transmission data" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the positions of the first target parallel sample data " in line 11-12. There are insufficient antecedent basis for these limitation in the claim.
Claim 3 recites the limitation "the timing" in line 13. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. The claim must be in one sentence form only. Claim 3 is formulated using two sentences, where second sentence starts in line 13. It is suggested to amend theses line as “…the timingand the adjusted first target parallel…”
Claim 3 recites the limitation "the adjusted first target parallel sample data" in line 13. There are insufficient antecedent basis for these limitation in the claim.
Claim 3 recites the limitation "the parallel bit sample data" in line 13-14. There are insufficient antecedent basis for these limitation in the claim.
Claim 3 recites the limitation “at least one data processing cycle” in line 14. It is unclear if this “at least one data processing cycle” is same or different from the “at least one data processing cycle” recited in line 9 and 10-11 in claim 1 upon which claim 3 indirectly depends on.
Claim 4 recites the limitation "M output delay circuits" in line 3. It is unclear if these "M output delay circuits" are same or different from “M output delay circuits” recited in line 1-2 in claim 2 upon which claim 4 depends on.
Claim 4 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. The claim must be in one sentence form only. Claim 4 is formulated using five sentences, where the second sentence starts in line 3, the third sentence starts at line 4, the fourth sentence starts in line 11 and the fifth sentence starts in line 15. It is suggested to amend theses line as “to M output delay circuitseach second serial and parallel conversion circuits correspond to N second”, “interpolation phasesthe data processing clock signal further”, “…interpolation phase[[.]] j is each integer value from “and “…the timingand the adjusted second target parallel…,” respectively.
Claim 4 recites the limitation "Each second serial and parallel conversion circuits" in line 3. It is unclear if these “Each second serial and parallel conversion circuits” are one of or different from the “M second serial and parallel conversion circuits” recited in line 2.
Claim 4 recites the limitation "the second data processing sub-clock signal" in line 4-5. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the ith second serial and parallel conversion circuit” in line 4-5. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if “the ith second serial and parallel conversion circuit" is one of the “M second serial and parallel conversion circuits” recited in line 2 or different from it.
Claim 4 recites the limitation “the jth second interpolation phase" in line 4-5. There is insufficient antecedent basis for this limitation in the claim. Further, it is unclear if “the jth second interpolation phase" is one of the “N second interpolation phases” recited in line 3-4 or different from it.
Claim 4 recites the limitation "the second data processing of the sub-clock signal" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the serial and parallel conversion" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the second preset number of bits" in line 8-9. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the second parallel sample data" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the second data rearrangement circuit" in line 13. There is insufficient antecedent basis for this limitation in the claim. It appears that “the second data rearrangement circuit” is being referred to “second rearrangement circuits” as recited in line 1-2 and depicted in Fig. 6. It is suggested to amend “second rearrangement circuits” as recited in line 1-2 as “second data rearrangement circuit[[s]]” to establish proper antecedent basis for "the second data rearrangement circuit" recited in line 13.
Claim 4 recites the limitation "the positions of the N second target parallel sample data" in line 13. There are insufficient antecedent basis for these limitation in the claim.
Claim 4 recites the limitation "the timing" in line 15. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the adjusted second target parallel sample data" in line 15. There are insufficient antecedent basis for these limitation in the claim.
Claim 4 recites the limitation "the parallel bit sample data" in line 16. There are insufficient antecedent basis for these limitation in the claim.
Claim 4 recites the limitation “at least one data processing cycle” in line 16. It is unclear if this “at least one data processing cycle” is same or different from the “at least one data processing cycle” recited in line 9 and 10-11 in claim 1 upon which claim 4 indirectly depends on.
Claim 5 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. The claim must be in one sentence form only. Claim 4 is formulated using five sentences, where the second sentence starts in line 2, the third sentence starts at line 3, the fourth sentence starts in line 7 and the fifth sentence starts in line 16. It is suggested to amend theses line as “third rearrangement circuitsthe third serial and parallel”, “the S third interpolation phasesthe data processing clock signal”, “the third data processing sub-clock signaland the interpolated transmission data” and “…the timingand the adjusted third target parallel” respectively.
Claim 5 recites the limitation "the S third interpolation phases" in line 3. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation "the third data processing sub-clock signal" in line 4. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation “each data processing cycle” in line 5-6. It is unclear if this processing cycle is same or different from the “at least one data processing cycle” recited in line 9 and 10-11 in claim 1 upon which claim 5 indirectly depends on.
Claim 5 recites the limitation "the kth third interpolation phase" in line 6. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation "the interpolated transmission data" in line 7. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation "in this data processing cycle" in line 8. It is unclear what “this” data processing cycle is being referred to.
Claim 5 recites the limitation "the serial and parallel conversion" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the third preset number of bits" in line 10-11. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the serial sample data" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the third parallel sample data" in line 11-12. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the third data rearrangement circuit" in line 14. There is insufficient antecedent basis for this limitation in the claim. It appears that “the third data rearrangement circuit” is referring to “third rearrangement circuits” as recited in line 2 and as depicted in Fig. 7. It is suggested to amend “third rearrangement circuits” as recited in line 2 as “third data rearrangement circuit[[s]]” to establish proper antecedent basis for "the second data rearrangement circuit" recited in line 14.
Claim 5 recites the limitation "the positions of the third target parallel sample data" in line 14. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation "the timing" in line 16. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the adjusted third target parallel sample data" in line 16. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation "the parallel bit sample data" in line 16. There are insufficient antecedent basis for these limitation in the claim.
Claim 5 recites the limitation “at least one data processing cycle” in line 17. It is unclear if this “at least one data processing cycle” is same or different from the “at least one data processing cycle” recited in line 9 and 10-11 in claim 1 upon which claim 5 indirectly depends on.
Claim 6 recites the limitation "receive original transmission data" in line 3. It is unclear what this “original transmission data” same or different from “original transmission data” recited in line 5 of claim 1, upon which claim 6 depends on. It is suggested to amend the limitation "receive original transmission data" in line 3 as "receive the original transmission data" to establish proper antecedent basis for “original transmission data” recited in line 5 of claim 1.
Claim 6 recites the limitation "the data transmitter" in line 5. There are insufficient antecedent basis for these limitation in the claim.
Claim 6 recites the limitation "the data buffer circuit" in line 6. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if “the data buffer circuit” is one of or different from “data buffer circuits” recited in line 1.
Claim 6 recites the limitation "and output it" in line 7. It is unclear if “it” is referring to “the original transmission data” or “the transmission data”.
Claim 6 recites the limitation "the signal compensation circuit" in line 8. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if “the signal compensation circuit” is one of or different from “signal compensation circuits” recited in line 2.
Claim 6 recites the limitation "and output it" in line 9. It is unclear if “it” is referring to “the original transmission data” or “the transmission data”.
Claim 7 recites the limitation " The device of any one of claim 2" in line 1. However, there is only one claim 2, hence it is unclear what “any one of” is referring to.
Claim 7 recites the limitation "the data selection circuit" in line 1. It is unclear if "the data selection circuit" is one of or different from “data selection circuits” recited in line 2 of claim 1, upon which claim 7 depends on.
Claim 7 recites the limitation "the data edge detection circuit" in line 3. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if “the data edge detection circuit” is one of or different from “data edge detection circuits” recited in line 1-2.
Claim 7 recites the limitation "the current data processing cycle" in line 5. There are insufficient antecedent basis for these limitation in the claim.
Claim 7 recites the limitation "the edge transition position" in line 6. There are insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the phase vote circuit" in line 7. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if "the phase vote circuit" is one of or different from “phase vote circuits” recited in line 2.
Claim 7 recites the limitation "the interpolation phase" in line 7. There are insufficient antecedent basis for these limitation in the claim. Further, it is unclear if " the interpolation phase" is same or different from “the ith first interpolation phase” recited in line 5-6 of claim 2 upon which claim 7 depends on.
Claim 7 recites the limitation "the data output circuit" in line 10. There are insufficient antecedent basis for these limitation in the claim. Further, it is unclear if "the data output circuit" is one of or different from “data output circuits” recited in line 2.
Claim 7 recites the limitation "the sample data" in line 10. There are insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the determined interpolation phase" in line 10-11. It is unclear if "the determined interpolation phase" is same or different from “the ith first interpolation phase” recited in line 5-6 of claim 2 upon which claim 7 depends on.
Claim 8 recites the limitation "the data selection circuit" in line 1. It is unclear if "the data selection circuit" is one of or different from “data selection circuits” recited in line 2 of claim 1, upon which claim 8 depends on.
Claim 8 recites the limitation "the data edge detection circuit" in line 3. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if “the data edge detection circuit” is one of or different from “data edge detection circuits” recited in line 1-2.
Claim 8 recites the limitation “each data processing cycle” in line 3. It is unclear if this processing cycle is same or different from the “at least one data processing cycle” recited in line 9 and 10-11 in claim 1 upon which claim 8 indirectly depends on.
Claim 8 recites the limitation "the current data processing cycle" in line 5. There are insufficient antecedent basis for these limitation in the claim.
Claim 8 recites the limitation "the edge transition position" in line 6. There are insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the phase vote circuit" in line 7. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if "the phase vote circuit" is one of or different from “phase vote circuits” recited in line 2.
Claim 8 recites the limitation "the interpolation phase" in line 7. There are insufficient antecedent basis for these limitation in the claim. Further, it is unclear if "the interpolation phase" is same or different from “the ith first interpolation phase” recited in line 5-6 of claim 2 upon which claim 8 indirectly depends on.
Claim 8 recites the limitation "the data output circuit" in line 10. There are insufficient antecedent basis for these limitation in the claim. Further it is unclear if “the data output circuit” is one of or different from “data output circuits” recited in line 2.
Claim 8 recites the limitation "the sample data" in line 10. There are insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the determined interpolation phase" in line 10-11. It is unclear if "the determined interpolation phase" is same or different from “the ith first interpolation phase” recited in line 5-6 of claim 2 upon which claim 8 depends on.
Claim 9 recites the limitation “each data processing cycle” in line 4. It is unclear if this processing cycle is same or different from the “each data processing cycle” recited in line 3 of claim 7 or “at least one data processing cycle” recited in line 9 and 10-11 in claim 1, upon which claim 9 indirectly depends on.
Claim 9 recites the limitation "the target data processing cycle" in line 4-5. There are insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the preset conditions" in line 5. There are insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the penultimate and last interpolation phases" in line 6. There are insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the first data output control instructions" in line 7. There are insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the sample data of the first and second interpolation phases" in line 6. There are insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the second data output control instructions" in line 7. There are insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation " The device of any one of claim 2" in line 1. However, there is only one claim 2, hence it is unclear what “any one of” is referring to.
Claim 12 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. The claim must be in one sentence form only. Claim 12 is formulated using two sentences, where the second sentence starts in line 2. It is suggested to amend this line as “temperature sensing control circuiteach output delay circuit includes multi-stage delay sub-circuit.”
Claim 12 recites the limitation "Each output delay circuit" in line 2. It is unclear if these "Each output delay circuits" are same or different from “M output delay circuits” recited in line 1-2 in claim 2 upon which claim 12 depends on.
Claim 12 recites the limitation "for each of the output delay circuits" in line 3. It is unclear if these “each of the output delay circuits" are same or different from “output delay circuit” recited in line 2 or “M output delay circuits” recited in line 1-2 in claim 2 upon which claim 12 depends on.
Claim 12 recites the limitation "the output delay circuit" in line 4. It is unclear if "the output delay circuit" is one of or different from “each of the output delay circuits” recited in line 3 or “M output delay circuits” recited in line 1-2 in claim 2 upon which claim 12 depends on.
Claim 12 recites the limitation "the multiplexer" in line 4. There are insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the corresponding delay sub-circuit" in line 5-6. There are insufficient antecedent basis for this limitation in the claim. Further, it is unclear if “the corresponding delay sub-circuit" is referring to “multi-stage delay sub-circuit” or is different from it.
Claim 12 recites the limitation "the changes in external temperature" in line 7. There are insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the delay sub-circuit" in line 8, 9 and 10. There are insufficient antecedent basis for this limitation in the claim. Further, it is unclear if these “delay sub-circuit" is referring to “multi-stage delay sub-circuit” or is different from it.
Claim 12 recites the limitation "the acquired temperature changes" in line 8. There are insufficient antecedent basis for this limitation in the claim. Further, it is unclear if “the acquired temperature changes" is referring to “the changes in external temperature” or is different from it.
Claim 13 recites the limitation " The device of any one of claim 4" in line 1. However, there is only one claim 4, hence it is unclear what “any one of” is referring to.
Claim 13 is rejected as failing to define the invention in the manner required by 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. The claim must be in one sentence form only. Claim 13 is formulated using two sentences, where the second sentence starts in line 2. It is suggested to amend this line as “temperature sensing control circuiteach output delay circuit includes multi-stage delay sub-circuit.”
Claim 13 recites the limitation "for each of the output delay circuits" in line 3. It is unclear if these “each of the output delay circuits" are same or different from “output delay circuit” recited in line 2 or “M output delay circuits” recited in line 1-2 in claim 2 upon which claim 13 indirectly depends on.
Claim 13 recites the limitation "the multiplexer" in line 4. There are insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the corresponding delay sub-circuit" in line 5-6. There are insufficient antecedent basis for this limitation in the claim. Further, it is unclear if “the corresponding delay sub-circuit" is referring to “multi-stage delay sub-circuit” or is different from it.
Claim 13 recites the limitation "the changes in external temperature" in line 7. There are insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the delay sub-circuit" in line 8, 9 and 10. There are insufficient antecedent basis for this limitation in the claim. Further, it is unclear if these “delay sub-circuit" is referring to “multi-stage delay sub-circuit” or is different from it.
Claim 13 recites the limitation "the acquired temperature changes" in line 8. There are insufficient antecedent basis for this limitation in the claim. Further, it is unclear if “the acquired temperature changes" is referring to “the changes in external temperature” or is different from it.
Claim 14 recites the limitation "A data recovery method that is applied to any one of data recovery circuit described in claim 1" in line 1-2. However, Claim 1 is a “circuit” claim which does not recite any “data recovery method,” process or steps. Therefore, it is unclear to which or what “data recovery method” are being referred to. Furthermore, it is unclear whether claim 14 intend to claim a method or an apparatus claim.
Claim 15 recites the limitation "A data recovery method that is applied to any one of data recovery circuit described in claim 12" in line 1-2. However, Claim 12 and claim 2, upon which claim 12 depends on, are “device” claims that do not recite any “data recovery method,” process or steps. Therefore, it is unclear to which or what “data recovery method” are being referred to. Furthermore, it is unclear whether claim 15 intend to claim a method or an apparatus claim.
Claims 2-13 recites in the preamble “The device of…” referring, directly or indirectly, back to 1, which recites “A circuit for data recovery data recovery applied to the data receiver, comprising clock generation, data reception, data oversampling, and data selection circuits…” It is unclear as to which or what “device” claims 2-13 are referring to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ho et al. (US 20120140812 A1) discloses (Abstract, Fig. 12, Para. [0070]) “details a double-data-rate (DDR) receiver 1200 in accordance with another embodiment adapted to accommodate margin shmooing. Receiver 1200 includes four data samplers 1205-1208 timed to an odd-phase clock Clk_O, four respective flip-flops 1210 timed to an even-phase clock Clk_E, three error-detecting XOR gates 1215, a multiplexer 1220, error-capturing logic 1225, and shmoo control logic 1230. An external tester (not shown) issues test instructions and receives margin-test results via a test-access port TAP. In another embodiment, the outputs from the three flip-flops 1210 following samplers 1205, 1206, and 1207 connect directly to corresponding inputs of multiplexer 1220. A single XOR gate on the output side of multiplexer 1220 then compares the selected sampler output signal with the output from sampler 1208.”
IQBAL et al. (US 20110170644 A1) discloses (Abstract, Fig. 9, 10, Para. [0077], [0082]) “a receiver 900 for receiving an input bit stream is shown, in accordance with an embodiment of the present invention. The receiver 900 includes a sampling unit 902, a multi-phase clock unit 904, a serial-to-parallel data converter 906, a clock divider unit 908, a clock and data recovery unit 910, and a resynchronization unit 912.” “Referring now to FIG. 10, a schematic block diagram illustrating the clock and data recovery unit 910 for recovering clock and data is shown, in accordance with an embodiment of the present invention. The clock and data recovery unit 910 includes a memory 1002, a glitch filter 1004, a non-transitioning phases identification unit 1006, a center phase identification unit 1008, a bit-wise transition vector calculation unit 1010, a final center phase selection unit 1012, a data recovery unit 1014, and an elasticity buffer 1016.”
Saeki et al. (US 20070073943 A1) discloses (Abstract, Fig. 1, 5, 6, Para. [0044]-[0045], [0048]) “FIG. 5 is a diagram showing the configuration of an example of the present invention. In FIG. 5, a register 120, a selector 121, a counter 122 and a counter 123 correspond to the register 1, selector 2, counter 3 and to the counter 4 of FIG. 1, respectively. In FIG. 5, a PLL 102, a divider 103, a phase interpolator 104, a sample circuit 105, a CDR controller 106, an output buffer 111, a pre-emphasis circuit 112 and a multiplexer 113 are the same as corresponding components already explained with reference to FIGS. 6 and 7 and hence the corresponding description is dispensed with.” “Two serial data signals from the sample circuit 105 of the clock and data recovery circuit is supplied to the register 120 and sampled by clock signals from the counter 122. Although no limitations are imposed on the clock signals from the counter 122, it may, for example, be five phase clocks of an even phase and five phase clocks of an odd phase of divided-by-10 ten phase clocks. The register 120 converts each of two serial data received from the sample circuit 105 into five-bit parallel data to output ten-bit parallel data RXDAT [9:0].” “[0048] During the pass-through time, the selector 121 outputs the two streams of serial data in the sequence in which the two streams of serial data from the sample circuit 105 of the clock and data recovery circuit have been received by the register 120, thereby implementing the FIFO function, along with the register 120. Meanwhile, if the selector 107 selects, as a read clock of the FIFO (a clock supplied to the counter 123), an output of the divider 103, that is, a clock obtained on dividing the output clock of the PLL circuit 102, based on the selection signal Sel1, the change-over of the clock is performed. The interface circuit shown in FIG. 5 may be used advantageously to a high-speed serial interface circuit between modules, such as DIMMs (Dual Inline Memory Modules)”
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633