DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 18/956,079 filed on 11/22/2024.
Claims 1-20 have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 6-12, 14-16, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jalal et al. (US 2019/0079868) and Li et al. (US 2024/0244013).
With respect to claim 1, Jalal teaches of a processor-implemented method for processor data sharing comprising: accessing a system-on-a-chip (SOC) (fig. 1; paragraph 15; where the system is a SOC),
wherein the SOC includes a network-on-a-chip (NOC) (fig. 1; paragraph 15; where the nodes are connected via the on-chip interconnect/network),
wherein the NOC includes coherent tiles (fig. 1; paragraph 18; where the request nodes (RNs) and home nodes (HN) are fully coherent and the I/O master nodes are I/O coherent);
dividing the NOC into a plurality of regions, wherein each region in the plurality of regions includes one or more coherent tiles (fig. 1; paragraph 15; each node can be considered a region);
initiating, by a first coherent tile within a first region within the plurality of regions, a snoop operation (fig. 1, 5; paragraph 43-44; where the home node (HN-F) sends a snoop to all nodes that share the data requested by RN-F);
generating, by the first coherent tile, a snoop vector for each region in the plurality of regions, wherein the snoop vector for each region selects at least one other coherent tile within the M x N mesh topology (fig. 1, 3-4; paragraph 19-20, 27, 38; where each entry (claimed snoop vector) of the snoop filter contains a tag field identifying the associated data/memory address. The snoop filter tracks the status of all the data stored in the caches in the nodes. Each entry also identifies the owner of any shared-dirty, or owned data as well as a presence vector that indicates which nodes of the system have the data in their local caches);
sending, by the first coherent tile, for each region in the plurality of regions, the snoop operation, wherein the sending is based on the snoop vector for each region (fig. 1, 5; paragraph 38, 43-44; where the home node (HN-F) sends a snoop to all nodes that share the data requested by RN-F according to the snoop filter entries (claimed snoop vector)); and
processing, by the at least one other coherent tile, the snoop operation (fig. 5; paragraph 44; where another RN-F node provides the data in response to the snoop).
Jalal fails to explicitly teach of (1) wherein the NOC includes an M x N mesh topology, wherein the M x N mesh topology includes a coherent tile at each point of the M x N mesh topology; (2) dividing the M x N mesh topology into a plurality of regions, wherein each region in the plurality of regions includes one or more coherent tiles.
However, Li teaches of accessing a system-on-a-chip (SOC), wherein the SOC includes a network-on-a-chip (NOC), wherein the NOC includes an M x N mesh topology, wherein the M x N mesh topology includes a coherent tile at each point of the M x N mesh topology (fig. 2, 5; paragraph 37-39, 112; where the NOC is a mesh topology as shown in the figures and allows for communication among the nodes/tiles that are located and each of the connection points of the mesh topology);
dividing the M x N mesh topology into a plurality of regions, wherein each region in the plurality of regions includes one or more coherent tiles (fig. 2, 5; paragraph 37-39, 112; where each node/tile can be considered a region);
Jalal and Li are analogous art because they are from the same field of endeavor, as they are directed to data management.
It would have been obvious to one of ordinary skill in the art having the teachings of Jalal and Li before the time of the effective filing of the claimed invention to incorporate the M x N mesh topology of the NOC of Li as the on-chip interconnect of Jalal. Their motivation would have been to more efficiently communicate between nodes.
With respect to claim 19, the combination of Jalal and Li teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Jalal also teaches of a computer program product embodied in a non-transitory computer readable medium for processor data sharing, the computer program product comprising code which causes one or more processors to generate semiconductor logic (fig. 1; paragraph 39, 57, 59, 61; where programmed instructions stored in computer storage are executed to establish functional logic blocks to carry out the disclosure).
With respect to claim 20, the combination of Jalal and Li teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Jalal also teaches of a computer system for processor data sharing comprising: a memory which stores instructions; one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to perform the disclosed operations (fig. 1; paragraph 39, 57, 59, 61; where programmed instructions stored in computer storage are executed to carry out the disclosed steps).
With respect to claim 2, Jalal teaches of wherein the snoop vector for each region includes a region ID (fig. 3; paragraph 27; where each entry in the snoop filter includes the owner node of any shared-dirty or owned data and the presence vector indicates which nodes of the system have the data in their local caches).
With respect to claim 3, Jalal teaches of wherein the region ID comprises one or more bits corresponding to each region in the plurality of regions (fig. 3; paragraph 27; where each entry in the snoop filter includes a presence vector that indicates which nodes of the system have the data in their local caches).
With respect to claim 4, Jalal teaches of wherein the sending includes every coherent tile within each region in the plurality of regions (paragraph 27, 35; where the snoop signals can be broadcast to all nodes).
With respect to claim 6, Jalal teaches of wherein the snoop vector for each region in the plurality of regions includes a region ID and a coherent tile ID (fig. 3; paragraph 27; where each entry in the snoop filter includes a presence vector that indicates which nodes of the system have the data in their local caches. The identification of a node in the presence vector is the claimed region ID and coherent tile ID since each tile/node is a region).
With respect to claim 7, Jalal teaches of identifying, with the region ID and the coherent tile ID, the at least one other coherent tile within the M x N mesh topology (paragraph 32, 44; where the nodes sharing the data are identified via the presence vector).
With respect to claim 8, Jalal teaches of wherein the identifying is based on a directory-based snoop filter (DSF) within the first coherent tile (fig. 1, 3; paragraph 19-20, 46; where the snoop filter is directory based).
With respect to claim 9, Jalal teaches of wherein the sending is accomplished with a unique clock cycle for each region in the plurality of regions (paragraph 35; where snooping the sharer nodes is performed one at a time. Thus suggests that sending each snoop would occur in different (unique) clock cycles as the prior snoop would have had to be sent and a response received for the next snoop to be sent).
With respect to claim 10, Jalal teaches of wherein the DSF determines a current owner of a cache line (fig. 3; paragraph 27; where each entry in the snoop filter identifies the owner of shared-dirty or owned data).
With respect to claim 11, Jalal teaches of wherein the DSF determines one or more sharers of a cache line (fig. 3; paragraph 27, 32; the presence vector in each snoop filter entry indicates which nodes share the data).
With respect to claim 12, Jalal teaches of wherein the DSF stores information pertaining to a specific address range (fig. 1; paragraph 15, 19-20; where the snoop filter in each home node maintains the status of the data stored in their system cache for a given set of memory addresses).
With respect to claim 14, Li teaches of wherein the coherent tile at each point of the M x N mesh topology comprises a switching unit (SU) (fig. 2, 5; paragraph 37; where each node/tile contains a router, item 22).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 15, Jalal teaches of wherein the first coherent tile includes a cache coherency block (CCB) and a coherency ordering agent (COA) (fig. 3-4; paragraphs 27, 38; the snoop filter is analogous to the cache coherency block and the snoop filter control logic is analogous to the coherency ordering agent).
With respect to claim 16, Jalal teaches of wherein the one or more other coherent tiles includes one or more I/O control interfaces (ICIs) (fig. 1; paragraph 39; as each node is connected to the on-chip interconnect, each node is connected to the interconnect via an interface).
With respect to claim 18, Jalal teaches of wherein the snoop operation is an invalidating snoop operation (table 2; paragraph 54-55; where the state of the data in node RNF0 is updated to ‘invalid’).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jalal and Li as applied to claim 1 above, and further in view of Deshpande (US 5,781,757).
With respect to claim 5, the combination of Jalal and Li fails to explicitly teach of wherein the sending is accomplished in a single clock cycle.
However, Deshpande teaches of wherein the sending is accomplished in a single clock cycle (fig. 9; column 8, line 15-column 9, line 14; where one processor broadcasts is coherence message in one cycle).
Jalal, Li, and Deshpande are analogous art because they are from the same field of endeavor, as they are directed to data management.
It would have been obvious to one of ordinary skill in the art having the teachings of Jalal, Li, and Deshpande before the time of the effective filing of the claimed invention to incorporate the sending a coherency message in a cycle in the combination of Jalal and Li as taught in Deshpande. Their motivation would have been to more quickly transmit messages.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jalal and Li as applied to claim 1 above, and further in view of Uehara et al. (US 2007/0156972).
With respect to claim 13, the combination of Jalal and Li fails to explicitly teach of wherein the sending is based on a region priority.
However, Uehara teaches of wherein the sending is based on a region priority (paragraph 4; where snoop requests are issued in the order of: the requesting node, the home node, and the caching node).
Jalal, Li, and Uehara are analogous art because they are from the same field of endeavor, as they are directed to data management.
It would have been obvious to one of ordinary skill in the art having the teachings of Jalal, Li, and Uehara before the time of the effective filing of the claimed invention to incorporate the sending out snoop in order of their destination node in the combination of Jalal and Li as taught in Uehara. Their motivation would have been to cause more efficient traffic on the network (Uehara, paragraph 4).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jalal and Li as applied to claim 1 above, and further in view of Yeager et al. (US 2019/0089619).
With respect to claim 17, the combination of Jalal and Li fails to explicitly teach of wherein the NOC includes a point-to-point packetized communication protocol.
However, Yeager teaches of wherein the NOC includes a point-to-point packetized communication protocol (paragraph 56; where the data packets transmitted across the NOC are sent point to point).
Jalal, Li, and Yeager are analogous art because they are from the same field of endeavor, as they are directed to data management.
It would have been obvious to one of ordinary skill in the art having the teachings of Jalal, Li, and Yeager before the time of the effective filing of the claimed invention to incorporate the point-to-point transmission of packets on the NOC in the combination of Jalal and Li as taught in Yeager. Their motivation would have been to more efficiently communicate between nodes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. (US 2015/0120998) discloses a SOC that contains a NOC where each node contains a node ID and sub-node ID, where the nodes are grouped by sub-node IDs.
Tune (US 2014/0281180) discloses a snoop directory that contains multiple snoop vectors.
Neiger et al. (US 6,112,283) discloses out of order snooping where snoop requests are ordered in an ordering buffer within each node.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138