Prosecution Insights
Last updated: August 30, 2026
Application No. 18/956,137

CONTROLLER FOR A RESONANT CONVERTER

Non-Final OA §102§103§112
Filed
Nov 22, 2024
Priority
Nov 22, 2023 — EU 23211426.4
Examiner
FINCH III, FRED E
Art Unit
Tech Center
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
737 granted / 918 resolved
+20.3% vs TC avg
Strong +18% interview lift
Without
With
+17.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
948
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
47.1%
+7.1% vs TC avg
§102
28.3%
-11.7% vs TC avg
§112
18.9%
-21.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 918 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office action is in response to the application and preliminary amendment filed on 22 November 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 9 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 9 further limits the controller of claim 1 by reciting that it is, “configured to use a constant fixed value instead of the measured current signal”. The use of “instead of” is understood to indicate that claim 9 does not include limitations regarding use of the measured current signal from its parent claim 1, and claim 9 is therefore in improper dependent form as failing to meet the requirements of the statute. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4-6, 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murata et al. (US 2020/0169176; hereinafter “Murata”). In re claims 1 and 13, Murata discloses a controller for a resonant converter (see resonant converter in Fig. 1 of Murata) and the corresponding control method (the control method claim 13 corresponds to the functional operations of the apparatus claim 1), the resonant converter comprising: a first switch and a second switch connected in series with each other between the supply source and a reference terminal (Fig. 1: switches Q1, Q2 in series between supply source Vi and its return terminal); and a resonant tank that is electrically connected to the first and second switches (Fig. 1: Lr, Lm, Cr connected to Q1, Q2), wherein the resonant tank comprises a resonant capacitor (Cr); wherein the controller is configured to: receive a measured voltage signal that represents the voltage at a predetermined point in the resonant tank (Fig. 1: control circuit 1 receives measured voltage Vcr being voltage across capacitor Cr); determine voltage-correction-signaling based on a measured current signal, which represents the current flowing in the resonant tank (Fig. 8: within control circuit 1, measured current signal IS is produced and used by load detection circuit 70 to determine voltage-correction-signaling as signal CA); and in response to the measured voltage signal crossing a voltage threshold value (Fig. 11: measured voltage Vcr is divided to representative voltage Vcr_d and then compared to thresholds Vth1 and/or Vth2 by comparators COMP11 and COMP12), after the application of the voltage-correction-signaling to either the measured voltage signal or the voltage threshold value as an offset (Fig. 12: voltage-correction-signaling CA is used by COMP13 and SW11/SW12 to change or offset the thresholds Vth1 and/or Vth2), change the state of the first switch and the second switch (Figs. 11 and 15: COMP11/COMP12 produce signals used to generate Vlow_b, Vhigh_b that are then used by logic circuit 40 (Fig. 15) to generate gate drive signals Vgs_lo, Vgs_hi to change the state of switches Q1, Q2; see [0098], [0099]). In re claim 4, Murata discloses wherein the controller is configured to: receive the measured voltage signal (Fig. 8: shunt circuit 60 of the controller receives measured voltage signal Vcr); and determine the measured current signal by calculating the differential of the measured voltage signal (Fig. 8: capacitor C21 is understood to perform a differential or derivative operation according to the known voltage/current relationship for a capacitor (current, I, equals capacitance, C, times the voltage derivative, dV/dt) to produce the measured current IS; see [0068]). In re claim 5, Murata discloses wherein the controller is configured to: determine the voltage-correction-signaling by multiplying the measured current signal by a compensation factor, which is a constant (Fig. 8 and [0070]-[0071]: voltage-correction-signaling CA is obtained from signal IS through the switching of SW1/SW2 and averaging on the capacitor C22; SW1 is turned on at the same duty cycle as main switch Q1 and thus the voltage-correction-signaling corresponds to current signal IS multiplied by the duty cycle). In re claim 6, Murata discloses wherein the controller is configured to: determine the value of a compensation-factor, for multiplying by the measured current signal to determine the voltage-correction-signaling (Fig. 8 and [0070]-[0071]: voltage-correction-signaling CA is obtained from signal IS through the switching of SW1/SW2 and averaging on the capacitor C22; SW1 is turned on at the same duty cycle as main switch Q1 and thus the voltage-correction-signaling corresponds to current signal IS multiplied by the duty cycle). In re claim 9, Murata discloses the controller configured to use a constant fixed value instead of the measured current signal (Fig. 8: obtaining the voltage-correction-signaling CA also uses the duty cycle of main switch Q1 via signal Vgd_hi, which is considered to be a constant fixed value used “instead of” the current signal). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Murata in view of Halberstadt (US 2011/0242856; hereinafter “Halberstadt”). In re claims 2 and 14, Murata discloses wherein the measured voltage signal represents the voltage at a predetermined point in the resonant tank (Fig. 1: control circuit 1 receives measured voltage Vcr being voltage across capacitor Cr); and either or both of: in response to the circuit 40 (Fig. 15) to generate gate drive signals Vgs_lo, Vgs_hi to change the state of switches Q1, Q2 when measured voltage Vcr crosses the thresholds; see [0098], [0099]); and ii) in response to the Murata does not disclose combining the voltage-correction-signaling with the measured voltage signal to provide corrected-voltage-signaling to be compared to the thresholds. Whereas Halberstadt discloses a resonant converter controller (Figs. 1, 2) in which a correction signal may be alternatively and equivalently applied to either of a measured capacitor voltage or to upper and lower thresholds to which the capacitor voltage is compared to generate switching signals (see Fig. 8, showing correction Voutcorr added to thresholds VcapH, VcapL at summers 74a/b; compare to equivalent control in Fig. 9, where Voutcorr is added to measured voltage Vcap at summer 84). The latter solution requires only a single summing circuit rather than two, as shown. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the controller of Murata by combining the voltage-correction-signaling with the measured voltage signal, rather than the thresholds, to provide corrected-voltage-signaling to be compared to the thresholds, as shown by Halberstadt, in order to reduce the amount of required circuitry. In re claim 3, Murata discloses receiving the measured current signal (Fig. 8: current signal IS). Murata does not disclose determining the measured voltage signal by integrating the measured current signal. Whereas Halberstadt discloses a resonant converter controller (Figs. 1, 2) in which a measured tank voltage signal is determined by integrating a measured tank current signal ([0071]-[0072]), in order to obtain the desired voltage in scenarios in which it is difficult to detect directly based on the layout of the resonant tank (id.). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the controller of Murata by determining the measured voltage signal by integrating the measured current signal in order to enable the desired voltage to be obtained even though it is difficult to obtain directly, based on resonant tank circuit layout in some implementations as taught by Halberstadt. Allowable Subject Matter Claims 7-8 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 7, the closest prior art in Murata as combined with Halberstadt discloses the invention according to claim 2 as explained above, but does not further disclose wherein the controller is configured to: determine a time error based on: the time difference between i) the measured voltage signal exceeding the upper voltage threshold value; and ii) the consequential opening of the first switch and the closing of the second switch; and / or the time difference between i) the measured voltage signal dropping below the lower voltage threshold value; and ii) the consequential opening of the second switch and the closing of the first switch; determine a compensation-factor based on the time error; and multiply the measured current signal by the compensation-factor to determine the voltage-correction-signalling. Murata does not contemplate determining such a time error based on time differences as claimed. Furthermore, the additional prior art on record also does not disclose such features, such that there is no suggestion found to modify Murata’s controller in a manner that could have achieved the claimed solution. Claim 8 depends from claim 7 and so would be allowable for the same reasons. With respect to claim 10, the closest prior art in Murata discloses the invention according to claim 1 as explained above, but does not further disclose wherein the controller is configured to: store, as a sampled-current-value, the value of the measured current signal at the instant in time that the voltage at the half-bridge node crosses half the supply the voltage for a preceding switching cycle; multiply the sampled-current-value by the compensation-factor to determine the voltage-correction-signalling. For instance, Murata does not disclose sampling the current value, much less at the specific time instant as claimed, nor multiplying such a sample by the correction factor. Furthermore, the additional prior art on record also does not disclose such features, such that there is no suggestion found to modify Murata’s controller in a manner that could have achieved the claimed solution. Claim 11 depends from claim 10 and so would be allowable for the same reasons. With respect to claim 12, the closest prior art in Murata as combined with Halberstadt discloses the invention according to claim 1 as explained above, but does not further disclose wherein the controller is configured to: add the voltage-correction-signalling to the measured voltage signal to provide a high-side-corrected-voltage-signal; subtract the voltage-correction-signalling from the measured voltage signal to provide a low-side-corrected-voltage-signal; in response to the high-side-corrected-voltage-signal exceeding the upper voltage threshold value, open the first switch and close the second switch; and in response to the low-side-corrected-voltage-signal dropping below the lower voltage threshold value, open the second switch and close the first switch. For instance, neither Murata nor Halberstadt disclose adding and subtracting the voltage-correction-signaling to the measured voltage signal to produce two distinct signals as recited in the claim. Furthermore, the additional prior art on record also does not disclose such features, such that there is no suggestion found to modify Murata’s controller in a manner that could have achieved the claimed solution. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2025/0070656 discloses HYSTERIC CONTROL FOR RESONANT CONVERTERS including adding a correction signaling to a measured tank capacitor voltage. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRED E FINCH III/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Nov 22, 2024
Application Filed
Jun 05, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
98%
With Interview (+17.9%)
2y 5m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 918 resolved cases by this examiner. Grant probability derived from career allowance rate.

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