DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Goel (US 2012/0242367 A1 hereinafter “Goel”) in view of Hargan (US 2010/0013512 A1 hereinafter “Hargan”).
As to claim 1, Goel discloses in Figs. 1, 2, 4 and 6:
A first die including a first test circuit (testing circuit 200 / TAP 410 / boundary scan sections 415 as shown in Figs. 2 and 4) (“The testing circuit 200 includes a first buffer 220 A and second buffer 215 A, each having a respective input and output coupled as shown to the input and output of a storage element 205 (latch or similar flip-flop device).”);
a second die including: (multiple level integrated circuit as shown in Figs. 1 and 4);
a through-silicon via (TSV) coupled to the first test circuit of the first die (TSV 130 as shown in Fig. 2) (“at least one of the input and output of the first buffer is electrically coupleable to respective multiple through-silicon vias (TSVs) to carry a signal in at least one of two opposite directions to and from the TSV”);
a first transistor including a first current terminal coupled to the TSV, wherein the first transistor includes a second current terminal (first buffer 220A having an input and an output as shown in Fig. 2) (“The testing circuit 200 includes a first buffer 220 A and second buffer 215 A, each having a respective input and output”).
Goel does not disclose a second transistor coupled to the second current terminal of the first transistor and a second test circuit coupled to the second current terminal of the first transistor.
However, Hargan discloses a second transistor coupled to the second current terminal of the first transistor and a second test circuit coupled to the second current terminal of the first transistor (transistors 208, 210, 212, 214 and sense amp 218 as shown in Fig. 2) (“connecting a first end of a series connected electrical through substrate via stack to the first reference by a second selected resistance coupled to a first transistor having a transistor resistance value; connecting a first end of each one of the series connected electrical through substrate via stacks through a second transistor to the first reference; connecting a second end of each one of the series connected electrical through substrate via stacks to be measured through a first input of a sense amplifier”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Goel and implement a second transistor coupled to the second current terminal of the first transistor and a second test circuit coupled to the second current terminal of the first transistor, as taught by Hargan for connecting the TSV current path through series transistors to a sense amplifier so that the stacked-die TSV path can be observed at the second current terminal.
As to claim 2,
Goel discloses wherein the first test circuit is configurable to deliver a stimulus signal to the TSV (flip-flop device 205 and first buffer 220A as shown in Fig. 2) (“the first buffers are switched on and the second buffers are switched off during the operation of inputting the value from the at least one flip-flop device into the multiple TSVs via the multiple first buffers”).
As to claim 3,
Hargan discloses wherein the second test circuit is configurable to receive a test signal from the second current terminal of the first transistor (sense amp 218 as shown in Fig. 2) (“a second sense amp input may be connected to a current source 222 and to the TSV stack, which may comprise one or more series connected TSVs”).
As to claim 4,
Hargan discloses wherein the second test circuit is configurable to compare the test signal to a voltage reference (sense amp 218 as shown in Fig. 2) (“One input of a sense amp 218 may be connected to a reference voltage (Vref) 202, and a second sense amp input may be connected to a current source 222 and to the TSV stack”).
As to claim 5,
Goel discloses wherein the first transistor includes a control terminal (enable of first buffer 220A as shown in Fig. 2), and wherein the second test circuit includes a flip-flop coupled to the control terminal of the first transistor (flip-flop device 205 as shown in Fig. 2) (“the flip-flop device 205 stores one bit of information and has an output Q that is electrically coupled to the input of the first buffer 220 A”).
As to claim 6,
Hargan discloses wherein the second test circuit includes a comparator coupled to the second current terminal of the first transistor (sense amp 218 as shown in Fig. 2) (“One input of a sense amp 218 may be connected to a reference voltage (Vref) 202, and a second sense amp input may be connected to a current source 222 and to the TSV stack, which may comprise one or more series connected TSVs”).
As to claim 7,
Hargan discloses wherein the second test circuit is configurable to determine that a resistance of the TSV is within an acceptable range (sense amp 218 and current source 222 as shown in Fig. 2) (“The voltage (VI) at the second input of sense amp 218 is a measure of the total TSV stack resistance (Rx).” “By driving stepped currents from 0.25 to 2.5 milliamps in 0.25 milliamp steps, the voltage measured at 218 may differ by more than 0.10 volts over a TSV stack resistance range of 5 ohms to 50 ohms, thus the value of the voltage at 218 provides a measurement of TSV quality.”).
As to claim 8,
Goel discloses wherein the first die includes a third switch coupled to the first test circuit and to the TSV (multiplexer 305A–C as shown in Fig. 6) (“further comprising at least one multiplexer having an input and an output, wherein the input of the at least one multiplexer is electrically coupled to the output of the at least one flip-flop device and a functional signal, wherein the output of the at least one multiplexer is electrically coupled to the input of the multiple first buffers”).
As to claim 9,
Goel discloses in Figs. 1, 2, 4 and 6:
a first die including:
a first test circuit (testing circuit 200 / TAP 410 / flip-flop device 205 as shown in Figs. 2 and 4) (“The testing circuit 200 includes a first buffer 220 A and second buffer 215 A, each having a respective input and output coupled as shown to the input and output of a storage element 205 (latch or similar flip-flop device).”);
and a through-silicon via (TSV) coupled to the first test circuit (TSV 130 as shown in Fig. 2) (“at least one of the input and output of the first buffer is electrically coupleable to respective multiple through-silicon vias (TSVs)”);
and a second die including:
a first transistor including a first current terminal coupled to the TSV of the first die, wherein the first transistor includes a second current terminal (first buffer 220A as shown in Fig. 2) (“The testing circuit 200 includes a first buffer 220 A and second buffer 215 A, each having a respective input and output”).
Goel does not disclose a second transistor coupled to the second current terminal of the first transistor and a second test circuit coupled to the second current terminal of the first transistor.
However, Hargan discloses a second transistor coupled to the second current terminal of the first transistor and a second test circuit coupled to the second current terminal of the first transistor (transistors 208, 210, 212, 214 and sense amp 218 as shown in Fig. 2) (“connecting a first end of each one of the series connected electrical through substrate via stacks through a second transistor to the first reference; connecting a second end of each one of the series connected electrical through substrate via stacks to be measured through a first input of a sense amplifier”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Goel and implement a second transistor coupled to the second current terminal of the first transistor and a second test circuit coupled to the second current terminal of the first transistor, as taught by Hargan for connecting the TSV current path through series transistors to a sense amplifier so that the stacked-die TSV path can be observed at the second current terminal.
As to claim 10,
Goel discloses wherein the first test circuit is configurable to deliver a stimulus signal to the TSV (flip-flop device 205 and first buffer 220A as shown in Fig. 2) (“the first buffers are switched on and the second buffers are switched off during the operation of inputting the value from the at least one flip-flop device into the multiple TSVs via the multiple first buffers”).
As to claim 11,
Hargan discloses wherein the second test circuit is configurable to receive a test signal from the second current terminal of the first transistor (sense amp 218 as shown in Fig. 2) (“a second sense amp input may be connected to a current source 222 and to the TSV stack, which may comprise one or more series connected TSVs”).
As to claim 12,
Hargan discloses wherein the second test circuit is configurable to compare the test signal to a voltage reference (sense amp 218 as shown in Fig. 2) (“One input of a sense amp 218 may be connected to a reference voltage (Vref) 202, and a second sense amp input may be connected to a current source 222 and to the TSV stack”).
As to claim 13,
Goel discloses wherein the first transistor includes a control terminal, and wherein the second test circuit includes a flip-flop coupled to the control terminal of the first transistor (enable of first buffer 220A and flip-flop device 205 as shown in Fig. 2) (“the flip-flop device 205 stores one bit of information and has an output Q that is electrically coupled to the input of the first buffer 220 A”).
As to claim 14,
Hargan discloses wherein the second test circuit includes a comparator coupled to the second current terminal of the first transistor (sense amp 218 as shown in Fig. 2) (“One input of a sense amp 218 may be connected to a reference voltage (Vref) 202, and a second sense amp input may be connected to a current source 222 and to the TSV stack, which may comprise one or more series connected TSVs”).
As to claim 15,
Hargan discloses wherein the second test circuit is configurable to determine that a resistance of the TSV is within an acceptable range (sense amp 218 as shown in Fig. 2) (“The voltage (VI) at the second input of sense amp 218 is a measure of the total TSV stack resistance (Rx).” “the value of the voltage at 218 provides a measurement of TSV quality.”).
As to claim 16,
Goel discloses wherein the first die includes a third switch coupled to the first test circuit and to the TSV (multiplexer 305A–C as shown in Fig. 6) (“the output of the at least one multiplexer is electrically coupled to the input of the multiple first buffers”).
As to claim 17,
Goel discloses in Figs. 2, 4 and 6:
a first die including a test circuit (testing circuit 200 / TAP 410 / flip-flop device 205 as shown in Figs. 2 and 4) (“The testing circuit 200 includes a first buffer 220 A and second buffer 215 A, each having a respective input and output coupled as shown to the input and output of a storage element 205 (latch or similar flip-flop device).”);
a through-silicon via (TSV) coupled to the test circuit (TSV 130 as shown in Fig. 2) (“at least one of the input and output of the first buffer is electrically coupleable to respective multiple through-silicon vias (TSVs)”);
and a second die including:
a first transistor including a first current terminal coupled to the TSV of the first die, wherein the first transistor includes a second current terminal and a control terminal (first buffer 220A as shown in Fig. 2) (“The testing circuit 200 includes a first buffer 220 A and second buffer 215 A, each having a respective input and output”);
a flip-flop coupled to the control terminal of the first transistor (flip-flop device 205 as shown in Fig. 2) (“the flip-flop device 205 stores one bit of information and has an output Q that is electrically coupled to the input of the first buffer 220 A”).
Goel does not disclose a second transistor coupled to the second current terminal of the first transistor and a comparator coupled to the second current terminal of the first transistor.
However, Hargan discloses a second transistor coupled to the second current terminal of the first transistor and a comparator coupled to the second current terminal of the first transistor (transistors 208, 210, 212, 214 and sense amp 218 as shown in Fig. 2) (“connecting a first end of each one of the series connected electrical through substrate via stacks through a second transistor to the first reference; connecting a second end of each one of the series connected electrical through substrate via stacks to be measured through a first input of a sense amplifier.” “One input of a sense amp 218 may be connected to a reference voltage (Vref) 202, and a second sense amp input may be connected to a current source 222 and to the TSV stack”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of Goel and implement a second transistor coupled to the second current terminal of the first transistor and a comparator coupled to the second current terminal of the first transistor, as taught by Hargan for connecting the TSV current path through series transistors to a sense amplifier so that the stacked-die TSV path can be observed at the second current terminal.
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As to claim 18,
Goel discloses wherein the test circuit is configurable to deliver a stimulus signal to the TSV (flip-flop device 205 and first buffer 220A as shown in Fig. 2) (“the first buffers are switched on and the second buffers are switched off during the operation of inputting the value from the at least one flip-flop device into the multiple TSVs via the multiple first buffers”).
Hargan discloses wherein the comparator is configurable to: receive a test signal from the second current terminal of the first transistor; and compare the test signal to a voltage reference (sense amp 218 as shown in Fig. 2) (“One input of a sense amp 218 may be connected to a reference voltage (Vref) 202, and a second sense amp input may be connected to a current source 222 and to the TSV stack”).
As to claim 19,
Hargan discloses wherein the comparator is configurable to determine that a resistance of the TSV is within an acceptable range (sense amp 218 as shown in Fig. 2) (“The voltage (VI) at the second input of sense amp 218 is a measure of the total TSV stack resistance (Rx).” “the value of the voltage at 218 provides a measurement of TSV quality.”).
As to claim 20,
Goel discloses wherein the first die includes a third switch coupled to the test circuit and to the TSV (multiplexer 305A–C as shown in Fig. 6) (“the input of the at least one multiplexer is electrically coupled to the output of the at least one flip-flop device and a functional signal, wherein the output of the at least one multiplexer is electrically coupled to the input of the multiple first buffers”).
Conclusion
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 9/4/26
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