Prosecution Insights
Last updated: July 17, 2026
Application No. 18/956,722

MULTILAYER ELECTRONIC COMPONENT

Non-Final OA §102§103§112
Filed
Nov 22, 2024
Priority
Dec 27, 2023 — RE 10-2023-0192144
Examiner
MCFADDEN, MICHAEL P
Art Unit
Tech Center
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
719 granted / 834 resolved
+26.2% vs TC avg
Strong +20% interview lift
Without
With
+20.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
13 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
87.4%
+47.4% vs TC avg
§102
8.9%
-31.1% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 834 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation of “an external electrode disposed on surfaces of the body opposing each other in a second direction” would imply that the external electrode is one external electrode that is formed to be on both ends of the capacitor but this should be 2 separate external electrodes and will be treated as such. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 6-8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2021/0065977). Regarding claim 1, Kim discloses a multilayer electronic component (Fig. 1-10), comprising: a body (Fig. 1, 110) including: a dielectric layer (Fig. 2, 111), first and second internal electrodes (Fig. 2, 121/122) alternately disposed in a first direction (Fig. 2, Z) with the dielectric layer interposed therebetween (Fig. 2), wherein a region of the body in which the first and second internal electrodes overlap in the first direction is referred to as a capacitance formation portion (Fig. 2, A), and a reinforcing portion (Fig. 2, C1) disposed on at least one of a first surface or a second surface of the capacitance formation portion opposing each other in the first direction; and an external electrode (Fig. 2, 131/132) disposed on surfaces of the body opposing each other in a second direction (Fig. 2, X) perpendicular to the first direction (Fig. 2), wherein the reinforcing portion includes a plurality of reinforcing patterns (Fig. 4, 141/142) including a plurality of conductive patterns (Fig. 5, 141’/142’) alternately disposed in the first direction and disposed in a grid shape (Fig. 5), and the plurality of conductive patterns are disposed to be spaced apart from surfaces of the body opposing each other in a third direction (Fig. 5, Y) perpendicular to the first direction and the second direction (Fig. 5), and at least a portion of the plurality of conductive patterns are in contact with the external electrode at both ends of the reinforcing portion in the second direction (Fig. 5). Regarding claim 2, Kim further discloses that, when a region of the body disposed on a third surface and a fourth surface of the capacitance formation portion in the second direction is referred to as a length-margin portion, an average length of the length-margin portion in the second direction is referred to as LM, and an average length of one conductive pattern among the plurality of conductive patterns in the second direction is referred to as D1, 0.35LM ≤ D1 ≤ 0.95LM is satisfied (Fig. 2-4, length of 141 is about half of the length of the internal electrode and therefore teaches this limitation). Regarding claim 3, Kim further discloses that, when an average length of one conductive pattern among the plurality of conductive patterns in the second direction is referred to as D1, and an average width of the conductive pattern in the third direction is referred to as D2, 0.35D1 ≤ D2 ≤ D1 is satisfied (Fig. 4, 141 is about a square so D2 and D1 would be about the same and therefore teach the claim limitation). Regarding claim 6, Kim further discloses that, when a maximum width of the body in the third direction is referred to as W, and a maximum width of one reinforcing pattern among the plurality of reinforcing patterns in the third direction is referred to as D5, 0.4W ≤ D5 ≤ 0.97W is satisfied (Fig. 4, 141 is more than half the width of the body). Regarding claim 7, Kim further discloses that the plurality of reinforcing patterns are alternately disposed with the dielectric layer interposed therebetween (Fig. 5). Regarding claim 8, Kim further discloses that, adjacent rows of reinforcing patterns among the plurality of reinforcing patterns do not overlap along the first direction (Fig. 2, only one row of 141 in C1 so it does not overlap with other rows). Regarding claim 10, Kim further discloses that, in a cross-section of the multilayer electronic component along the first and third directions, the plurality of conductive patterns overlap a central portion of the capacitance formation portion (Fig. 4). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2021/0065977). Regarding claim 4, Kim fails to teach the claim limitations. However, the examiner notes that the limitation of “wherein, when a length, in the second direction, of a space between adjacent conductive patterns among the plurality of conductive patterns is referred to as D3, 0.5 µm ≤ D3 ≤ 80µm is satisfied” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein, when a length, in the second direction, of a space between adjacent conductive patterns among the plurality of conductive patterns is referred to as D3, 0.5 µm ≤ D3 ≤ 80µm is satisfied” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Regarding claim 5, Kim fails to teach the claim limitations. However, the examiner notes that the limitation of “wherein, when a length, in the third direction, of a space between adjacent conductive patterns among the plurality of conductive patterns is referred to as D4, 0.05µm ≤ D4 ≤ 80µm is satisfied” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein, when a length, in the third direction, of a space between adjacent conductive patterns among the plurality of conductive patterns is referred to as D4, 0.05µm ≤ D4 ≤ 80µm is satisfied” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2021/0065977) in view of Lee et al (US 2016/024311). Regarding claim 9, Kim fails to teach the claim limitations. Lee teaches that, in a cross-section of the multilayer electronic component along the first and second directions (Fig. 2, T and L), the plurality of conductive patterns (Fig. 2, 143/141/142) overlap a central portion of the capacitance formation portion (Fig. 2, at center in L direction). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Lee to the invention of Kim, in order to provide a multilayer ceramic electronic component capable of securing bending strength while having high capacitance ([0008]). Allowable Subject Matter Claims 11-20 would be allowed if the 112 rejection was overcome. The following is an examiner’s statement of reasons for allowance: Regarding independent claim 11, the prior art fails to teach or suggest, alone or in combination: A multilayer electronic component, comprising: a body including: a dielectric layer, first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween in a first direction, wherein a region of the body in which the first and second internal electrodes overlap in the first direction is referred to as a capacitance formation portion, and a reinforcing portion disposed on at least one of a first surface or a second surface of the capacitance formation portion opposing each other in the first direction; and an external electrode disposed on surfaces of the body opposing each other in a second direction perpendicular to the first direction, wherein the reinforcing portion includes a first reinforcing pattern and a second reinforcing pattern not overlapping the first reinforcing pattern in the first direction, the first reinforcing pattern includes a plurality of 1-1 conductive patterns disposed to be spaced apart from each other in the second direction and a third direction perpendicular to the first direction and the second direction, and a plurality of 1-2 conductive patterns disposed between spaces by which adjacent 1-1 conductive patterns among the plurality of 1-1 conductive patterns are spaced apart in the second direction, the plurality of 1-2 conductive patterns are disposed to be spaced apart from each other in the second direction and the third direction, and the second reinforcing pattern includes a plurality of 2-1 conductive patterns disposed to be spaced apart from each other in the second direction and the third direction, and a plurality of 2-2 conductive patterns disposed between spaces by which adjacent 2-1 conductive patterns among the plurality of 2-1 conductive patterns are spaced apart in the second direction, the plurality of 2-2 conductive patterns are disposed to be spaced apart from each other in the second direction and the third direction. Specifically, the prior art fails to teach or make obvious, alone or in combination, the limitation of “the first reinforcing pattern includes a plurality of 1-1 conductive patterns disposed to be spaced apart from each other in the second direction and a third direction perpendicular to the first direction and the second direction, and a plurality of 1-2 conductive patterns disposed between spaces by which adjacent 1-1 conductive patterns among the plurality of 1-1 conductive patterns are spaced apart in the second direction, the plurality of 1-2 conductive patterns are disposed to be spaced apart from each other in the second direction and the third direction, and the second reinforcing pattern includes a plurality of 2-1 conductive patterns disposed to be spaced apart from each other in the second direction and the third direction, and a plurality of 2-2 conductive patterns disposed between spaces by which adjacent 2-1 conductive patterns among the plurality of 2-1 conductive patterns are spaced apart in the second direction, the plurality of 2-2 conductive patterns are disposed to be spaced apart from each other in the second direction and the third direction” in combination with the other claim limitations. Additional Relevant Prior Art: MA et al (US 2013/0335882) teaches relevant art in Fig. 8. Choi et al (US 2022/0238274) teaches relevant art in Fig. 2. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P MCFADDEN/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Nov 22, 2024
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683082
MULTILAYER CERAMIC CAPACITOR
2y 3m to grant Granted Jul 14, 2026
Patent 12683090
ELECTROLYTIC CAPACITOR ELEMENT AND ELECTROLYTIC CAPACITOR
1y 10m to grant Granted Jul 14, 2026
Patent 12683086
ELECTROLYTIC CAPACITOR
1y 10m to grant Granted Jul 14, 2026
Patent 12671030
MULTILAYER ELECTRONIC COMPONENT
2y 6m to grant Granted Jun 30, 2026
Patent 12671036
MULTILAYER CERAMIC CAPACITOR
2y 2m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+20.0%)
2y 2m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 834 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month