DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2024 was considered by the examiner.
Drawings
The drawings received on 11/22/2024 have been accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHO [US 2024/0061591].
Claim 1, CHO discloses a storage system including a storage apparatus [1000, Fig 1] that saves data in accordance with a data input/output request from a host or outputs the saved data [par. 0031], the storage system comprising:
a plurality of components each configured to operate in a first power mode or at least one second power mode in a switchable manner [par. 0009], the second power mode consuming less power than the first power mode [switching from regular power mode to low power mode, par. 0036];
a condition monitoring section that monitors an operating condition of each of the plurality of components; and a power mode control section that determines a power mode of at least one particular component to be the second power mode [memory power mode controller 20, par. 0030], according to a processing load which is related to each of the plurality of components and which corresponds to a result of monitoring by the condition monitoring section [counting idle time, par. 0036], and operates the at least one particular component in the second power mode [low power mode, par. 0036], wherein
the power mode control section compares power consumption in a first case where the power mode of a component with a high predicted processing load is set to a predetermined second power mode and where the power mode of a component with a low predicted processing load is set to a particular second power mode with power consumption in a second case where the power mode is determined for each component, and on condition that the power consumption in the second case is greater than the power consumption in the first case, sets the power mode of the component with the high predicted processing load to the predetermined second power mode, and sets the power mode of the component with the low predicted processing load to the particular second power mode, and the plurality of components perform mutual control with the storage apparatus in accordance with the data input/output request [par. 0030-0032].
Claim 2, CHO discloses the storage system according to claim 1, wherein the plurality of components are a plurality of sub elements of each of processors of a plurality of controllers, and, while one of the processors of one of the controllers is in operation, control of some of the sub elements by the one of the processors is switched to the other processor of the other controller, the power mode of the one of the processors is set to the particular second power mode, and the power mode of the other processor is set to the predetermined second power mode consuming greater power than the particular second power mode [memory power mode controller, power mode switching, par. 0036-0037 and 0044-0046].
Claim 3, CHO discloses the storage system according to claim 2, wherein the power mode control section performs switching in such a manner that the other processor controls the data input/output request from the host by using the sub element of the one of the controllers [par. 0009, 0036-0038].
Claim 4, CHO discloses the storage system according to claim 3, wherein the storage apparatus includes a control queue [collection of chips, par. 0009], and the other processor accesses the control queue when controlling the data input/output request [access request, 0009] from the host by using the sub element of the one of the controllers [par. 0031-0033].
Claim 5, CHO discloses the storage system according to claim 2, wherein the power mode control section causes, by transmitting a predetermined interrupt via the one of the processors [clock gating, par. 0096-0098, 0100], the other processor to access the sub element constituting a part of the one of the processors after clock restart [par. 0008].
Claim 6 is rejected using the same rationale as Claim 1 wherein Claim 6 represent the method of the product structure of Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheong [US 11,995,348]; Data and Power Management of Partitioned Bufffer in a Storage Device. Col. 7, lines 18-26.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133