DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application is being examined under the pre-AIA first to invent provisions.
Status of Claims
2. Claims 1-20 are presented for examination.
Drawings
3. The correction drawings received on 06/10/2026 are acceptable for examination purposes. Therefore, the objection is withdrawn.
Response to Arguments
4. Applicant’s argument filed on 06/10/2026 with respect claims 1-20 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of "a test access port (TAP) circuit coupled to the TCK input and to the TMS input." As recited in claims 1 and 11.
The Examiner respectfully disagrees and asserts the reference of Whetsel (US 2008/0250287 A1) in paragraphs [0009], [0051], [0247], and Fig. 50 teaches such limitation. For example, the test interface 104 includes a test access port (TAP) state machine controller and signals TDI, TCK, TMS, TRST, and TDO. The test architecture 102 includes an instruction register and a set of selectable data registers. As seen in FIG. 1, the data registers consists of various types including but not limited too, a boundary scan register, digital test registers, debug/emulation registers, programming registers, mixed signal test registers, and a bypass register. The TAP receives a test clock (TCK), test mode select (TMS), and test reset (TRST) input signals. The TAP responds to the TCK and TMS input signals to shift data through either the instruction register or a selected data register from the test data input (TDO) signal to the test data output (TDO) signal. The TAP has proven to be an efficient and popular test control interface for ICs and cores. See paragraph [0009].
As seen in FIG. 46, each of the TAP based standards included in circuit 4602 advantageously share a common TAP 318 interface and architecture 4604. The architecture 4604 includes a commonly shared instruction register 314, a commonly shared set of selectable data registers 316, commonly shared gating circuitry 308, and commonly shared instruction 302 and data 304 control buses to the commonly shared TAP 318. The external TAP test bus 4608 is achieved using 5 signals (TDI, TDO, TCK, TMS, and TRST). Regardless of whether circuit 4602 is a core or an IC, these 5 signals are dedicated and reserved for use in accessing the TAP to perform testing or other operations with the common architecture 4604. The availability of the dedicated TAP test bus has proven very beneficial since it provides non-intrusive access to a functionally operating circuit 4602 to perform real time test, emulation, debug, and other operations. The dedicated TAP test bus has also lead to an ever increasing set of TAP interface support tools supporting test, emulation, debug, programming, and other TAP based operations. See pargrapg [0051].
In FIG. 83A, Bus A 8338 represents the TMS, TCK, and TRST inputs to the Tap controller 318. See paragraph [0247]. Also see Fig. 50 printed below for your convenience that show the test access port (TAP) circuit 318 coupled to the TCK input and to the TMS input. “Emphasis added.”
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As described above in Fig. 50, it’s clear that Whetsel teaches a test access port (TAP) circuit coupled to the TCK input and to the TMS input." “Emphasis added.
Also, applicant contends that the cited references fail to teaches or suggest the limitation of “a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit.” As recited in claims 1 and 11.
The Examiner notes that the applicant’s arguments regarding to the above limitation has been considered but is moot in view of the new ground(s) of rejection. In addition to, the Examiner maintains the reference of Whetsel (US 2008/0250287 A1) since there is no further argument/s regarding to this reference.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claim 1-3 and 11-14 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Whetsel (US 2008/0250287 A1) “herein after as Whetsel ‘287” in view of (US 2008/0281546 A1) “herein after as Whetse ‘546.”
As per claim 1:
Whetsel ‘287 substantially teaches or discloses a device comprising (see Fig. 50, merged architecture 4904) : a test clock (TCK) input (see Fig. 50, TCK input); a test mode select (TMS) input (see Fig. 50, TMS input); a test data in (TDI) input (see Fig. 50, TDI input); a test data out (TDO) output (see Fig. 50, TDO output); an instruction register (see Fig. 50, instruction register 314) coupled to the TDI input and to the TDO output (see Fig. 50, the instruction register 314 coupled to the TDI input and to the TDO output); a test access port (TAP) circuit coupled to the TCK input and to the TMS input (see paragraph 247], herein in FIG. 83A, Bus A 8338 represents the TMS, TCK, and TRST inputs to the Tap controller 318, and Fig. 50); a first routing circuit (see Fig. 50, gating circuit 5004) coupled to the instruction register (see Fig. 50, instruction register 314) and [ ] (see Fig. 50, TAP 318); and a first data register (see Fig. 50 data register 1) coupled to the first routing circuit (see Fig. 50, gating circuit 5004).
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Whetsel ‘287 does not explicitly teach a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit; and a first routing circuit coupled to the command circuit.
However, Whetsel ‘546 in analogous art teaches a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit (see Figs, 9 & 30, the address circuit 906 coupled to the TCK input and to the TMS input, 30, 34, and in 39 the Address & Command Circuit 3102 coupled to the TCK input and to the TMS input); and the first routing circuit (see Fig. 39, TAP Linking Circuit 4004) coupled to the command circuit (see Fig. 39, TAP Linking Circuit 4004 is coupled to the Address & Command Circuit 3502 via command bus 3108).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the communication system of Whetsel ‘287 with the teachings of Whetsel ‘546 by including a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit; and a first routing circuit coupled to the command circuit.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit; and a first routing circuit coupled to the command circuit would have improved the test system performance.
As per claim 2:
Whetsel ‘287 teaches that a second routing circuit (see Fig. 54, gating 308) coupled to the instruction register (see Fig. 54 instruction register 314) and to the command circuit (see Fig. 54, TAP 318); and a second data register (see Fig. 54, data registers 1202) coupled to the second routing circuit (see Fig. 54, gating 308).
As per claim 3:
Whetsel 546 teaches that wherein the TAP circuit includes a state machine circuit (see Fig. 34, TAP state machine 910) coupled to the TCK input, the TMS input (see Fig. 34 TCK & TMS inputs), and the command circuit (see Fig. 34, Address Circuit 3102).
As per claim 11:
Whetsel ‘287 substantially teaches or discloses a system comprising: a daisy chain of devices including (see Fig. 50) a first device (see Fig. 50, architecture 4904) and a second device (see Fig. 50, merged test interface 4906); a clock input coupled to the first device and to the second device (see Fig. 50); a test clock (TCK) input coupled to the first device and to the second device (see Fig. 50, TCK input); a test mode select (TMS) input coupled to the first device and to the second device (see Fig. 50, TMS input); wherein the first device includes (see Fig. 50, architecture 4904): an instruction register (see Fig. 50, instruction register 314) a test access port (TAP) circuit coupled to the TCK input and to the TMS input (see paragraph 247], herein in FIG. 83A, Bus A 8338 represents the TMS, TCK, and TRST inputs to the Tap controller 318, and Fig. 50); a first routing circuit (see Fig. 50, gating circuit 5004) coupled to the instruction register (see Fig. 50, instruction register 314) [ ]; and a first data register (see Fig. 50 data register 1) coupled to the first routing circuit (see Fig. 50, gating circuit 5004). Whetsel ‘287 does not explicitly teach a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit; and the first routing circuit coupled to the command circuit.
However, Whetsel ‘546 in analogous art teaches a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit (see Figs, 9 & 30, the address circuit 906 coupled to the TCK input and to the TMS input, 30, 34, and in 39 the Address & Command Circuit 3102 coupled to the TCK input and to the TMS input); and the first routing circuit (see Fig. 39, TAP Linking Circuit 4004) coupled to the command circuit (see Fig. 39, TAP Linking Circuit 4004 is coupled to the Address & Command Circuit 3502 via command bus 3108).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the communication system of Whetsel ‘287 with the teachings of Whetsel ‘546 by including a command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit; and a first routing circuit coupled to the command circuit.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the command circuit coupled to the TCK input and to the TMS input, wherein the command circuit is separate from the TAP circuit; and a first routing circuit coupled to the command circuit would have improved the test system performance.
As per claim 12:
Whetsel ‘287 teaches that wherein the first device includes a test data out (TDO) output (see Fig. 50 TDO) coupled to the instruction register (see Fig. 50, instruction register 308) and wherein the second device (see Fig. 50, merged test interface 4906) includes a test data in (TDI) input (see Fig. 50 TDI input) coupled to the TDO output of the first device (see Fig. 50 TDO).
As per claim 13:
Whetsel ‘287 teaches that wherein the first device includes (see Fig. 54): a second routing circuit (see Fig. 54, gating 308) coupled to the instruction register (see Fig. 54 instruction register 314) and to the command circuit (see Fig. 54, TAP 318); and a second data register (see Fig. 54, data registers 1202) coupled to the second routing circuit (see Fig. 54, gating 308).
As per claim 14:
Whetsel ‘546 teaches that wherein the TAP circuit includes a state machine circuit (see Fig. 34, TAP state machine 910) coupled to the TCK input, the TMS input (see Fig. 34 TCK & TMS inputs), and the command circuit (see Fig. 34, Address Circuit 3102).
6. Claim 10 and 20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Whetsel (US 2008/0250287 A1) “herein after as Whetsel ‘287” in view of (US 2008/0281546 A1) “herein after as Whetse ‘546” in further view of Benedix et al. (US 20040151037 A1) “herein after as Benedix.”
As per claims 10 and 20:
Whetsel ‘287-Whetsel ‘546 as combined does not teaches a test compression architecture including the first data register.
However, Benedix in analogous art teaches a test compression architecture including the first data register (see paragraph [0023], herein the test data compression circuit contains a plurality of test data compression circuit modules which each have a test data register for storing a test data sequence read from the memory cell array via a data line in the test data bus).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the communication system of Whetsel ‘287-Whetsel ‘546 as combined with the teachings of Benedix by including the test compression architecture including the first data register.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the test compression architecture including the first data register would have improved the data reliability of the test system.
Allowable Subject Matter
7. Claims 4, 5 and 15, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claims 6-9 and 17-19 is/are dependent from allowable independent claims 5 and 16 respectively and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
8. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
9. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069.
The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
Prosecution Insights