DETAILED ACTION
This action is in response to the preliminary amendment filed on 12/10/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, 9, and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kodaka et al. (“Power Decoupling Method Using Input Filters in a Matrix Converter for Isolated AC/DC Converters Fed by Single or Three-Phase Supply”). Regarding claim 1 and 19, Kodaka et al. discloses (see fig. 1) a power converter arrangement comprising: an input filter (Input Filter) configured to couple to a first phase terminal of a single-phase power network (connection to single phase source) wherein the input filter is configured to: receive a first alternating current (AC) voltage (connection of Input Filter to single phase Vin) and filter the first AC voltage to provide an input voltage (operation and output from Input Filter); an electrical switching network (Sru, Srv, Stu, Stv, and output terminal of network) comprising: an output terminal (output to resonant circuit); an array of bidirectional switches (Sru, Srv, Stu, Stv) configured to generate a switched voltage from the input voltage at the output terminal (operation of Sru, Srv, Stu, Stv); and a decoupling capacitor (see capacitor in Power Decoupling Circuit) configured to reduce undesirable oscillations at the output terminal (operation of capacitor in Power Decoupling Circuit); and a resonant circuit (Cr, Lr, transformer, output rectifier) configured to convert the switched voltage into a supply voltage for supplying a load (operation of Cr, Lr, transformer, output rectifier). Regarding claim 5, Kodaka et al. discloses (see fig. 1) that the electrical switching network (Sru, Srv, Stu, Stv,) further comprises a plurality of branches (branches comprising Sru, Srv, Stu, Stv,) of bidirectional switches, wherein the branches are connected in parallel to form legs of the electrical switching network (see parallel connection of branches), and wherein the decoupling capacitor (140) is connected to a midpoint of one of the legs of the electrical switching network (see connection of capacitor in the Power Decoupling Circuit). Regarding claim 6, Kodaka et al. discloses (see fig. 1) that the plurality of branches (see branches comprising Sru, Srv, Stu, Stv) comprises a first branch connected to which the decoupling capacitor (connection of branch to capacitor in the Power Decoupling Circuit) is connected, and wherein the first branch forms a decoupling branch for decoupling the undesirable oscillations at the output terminal (operation of branch connected to the capacitor). Regarding claim 7, Kodaka et al. discloses (see fig. 1) that the electrical switching network (Sru, Srv, Stu, Stv) further comprises: a first input node (first input connection to switching network) and a second input node (second input connection to switching network) each configured to receive the input voltage (connection to Vin);a first output node (first output connection from switching network) and a second output node (second output connection from switching network) each configured to provide the switched voltage (output from switching network); a first branch (branch comprising Sru, Srv) of bidirectional switches and a second branch (branch comprising Stu, Stv) of bidirectional switches connected in parallel between the first output node and the second output node (see parallel connection of two branches); and a decoupling branch (see Power Decoupling Circuit) of bidirectional switches connected in parallel to the first branch and the second branch of bidirectional switches between the first output node and the second output node (see parallel connection of two branches and the Power Decoupling Circuit),wherein the decoupling capacitor (see capacitor in Power Decoupling Circuit) is connected to the decoupling branch (connection to Power Decoupling Circuit branch). Regarding claim 9 and 20, Kodaka et al. discloses (see fig. 1) a power converter arrangement comprising: an input filter (Input Filter ) comprising a first input filter capacitor (see capacitor in the Input Filter), wherein the input filter is configured to: couple to a plurality of phase terminals of a multi-phase power network to receive a respective alternating current (AC) voltage (see connection of Input Filter to three-phase source), wherein each of the phase terminals is configured to provide the AC voltage with a different voltage phase (see three-phase), wherein at least one phase terminal of the multi- phase power network is a non-operational phase terminal (operation of switches disconnecting one of the phases); and filter the respective AC voltage to provide a respective input voltage (operation and output from Input Filter); an electrical switching network (Sru, Srv, Stu, Stv, and output terminal of network) comprising: an output terminal (output to resonant circuit), wherein the first input filter capacitor is configured to reduce undesirable oscillations at the output terminal (operation of capacitor removing ripple); and an array of bidirectional switches (Sru, Srv, Stu, Stv) configured to generate a switched voltage from the respective input voltages at the output terminal (operation of Sru, Srv, Stu, Stv); and a resonant circuit (Cr, Lr, transformer, output rectifier) configured to convert the switched voltage into a supply voltage for supplying a load (operation of Cr, Lr, transformer, output rectifier).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kodaka et al. (“Power Decoupling Method Using Input Filters in a Matrix Converter for Isolated AC/DC Converters Fed by Single or Three-Phase Supply”) in view of Vadhavkar et al. (US Patent 9973102). Regarding claim 12, Kodaka et al. does not disclose that the input filter comprises input filter capacitors, wherein the input filter capacitors comprise the first input filter capacitor, and wherein the input filter capacitors are configured to couple to the phase terminals. Vadhavkar et al. discloses (see fig. 1) that the input filter (20) comprises input filter capacitors (C1-C3), wherein the input filter capacitors comprise a first input filter capacitor (C1), and wherein the input filter capacitors are configured to couple to phase terminals (see connection of C1-C3 to phase terminals). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter arrangement of Kodaka et al. to include the features of Vadhavkar et al. because it provides for a filtering means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 13, Kodaka et al. does not disclose that the input filter capacitors (242, 241, 240) are interconnected in a Y-configuration or in a Delta-configuration. Vadhavkar et al. discloses that the input filter capacitors (C1-C3) are interconnected in a Y-configuration or in a Delta-configuration (Column 3 line 54-59). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter arrangement of Kodaka et al. to include the features of Vadhavkar et al. because it provides for a filtering means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Allowable Subject Matter
Claims 2-4, 8, 10-11, and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Wijekoon et al. (US 2024/0039400) discloses a matrix power converter and method for use. Everts (US 2023/0155518) discloses an electrical power converter and method thereof.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A GBLENDE whose telephone number is (571)270-5472. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838