DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see REMARKS, filed 07/30/2026, with respect to claims 14-16 and 18 have been fully considered and are persuasive in view of the filed amendments. The rejection of claims 14-16 and 18 has been withdrawn.
The Office notes that no replacement drawing of Fig. 2B has been received in the recent filling contrary to applicants remark of doing so (see REMARKS pg. 8). Therefore, the Office maintains its objection to the drawing as below.
Applicant's arguments filed 07/30/2026, with respect to claims 1-2, 4-13 have been fully considered but they are not persuasive.
Applicants states (see REMARKS pg. 8) “Applicant further submits that the amendments to the pending claims have placed these claims in condition for allowance.”
The Office respectfully disagrees. Amendment of claim 1 is not of the scope to that as indicate allowable since amended claim 1 is not “rewritten in independent form including all of the limitations of the base claim and any intervening claims.” In other words, limitations of claim 2 are not included in amended claim 1, which was an intervening claim of claim 3 that has been now amended into original claim 1.
Upon further search and consideration, amended claim 1 is not allowable as detailed below.
Drawings
The drawings are objected to because Figure 2B is illegible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4 and 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 20040229592 A1) further in view of Khalaf et al. (NPL titled: "Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication," in IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1579-1592, July 2016).
Regarding Claim 1, Matsui et al. discloses;
A digital polar transmitter (Fig. 1, 4, 5) with improved transmission behavior, comprising:
a first modulating unit (Fig. 1: 211a, LPF1, MIXa1), especially a first phase modulating unit (Fig. 1: 211a modulates I-phase), with a first variable gain being controllable with the aid of a first phase-referred signal (Fig. 1, Para. [0041], [0045]: “a first amplifying unit 211 comprising gain variable amplifiers 211a…which amplify I-signals…” “control voltages Vc1[first phase-referred signal]...for controlling gain are supplied from the baseband LSI 300 to the gain variable amplifiers 211a”),
a second modulating unit (Fig. 1: 211b, LPF2, MIXa2), especially a second phase modulating unit (Fig. 1: 211a modulates Q-phase) , with a second variable gain being controllable with the aid of second phase-referred signal (Fig. 1, Para. [0041], [0045]: “a first amplifying unit 211 comprising gain variable amplifiers…211b…which amplify…Q-signals…” “control voltages Vc1[second phase-referred signal]...for controlling gain are supplied from the baseband LSI 300 to the gain variable amplifiers…211b”),
a third modulating unit (Fig. 1, 4, 5: power amplifier 411), especially an amplitude modulating unit (Fig. 1, 4, 5, Para. [0047]: power amplifier 411 where “the output level [amplitude] is raised and lowered by controlling the gain of … the power amplifiers 411…), with a third variable gain being controllable with the aid of an amplitude-referred signal (Fig. 1, 4, 5, Para. [0047]: “the control voltage Vc3 [amplitude-referred signal]…the output level is raised and lowered by controlling the gain of…the power amplifiers 411…”), and
…forming the sum of an output of the first modulating unit and an output of the second modulating unit and providing the sum at an adding unit output (Fig. 1, 4, 5: an output of MIXa1 and an output of MIXa2 are combined and provided at an output node),
wherein the first phase-referred signal and the second phase-referred signal are synchronized (Fig. 1, 4, 5, Para. [0051]: control voltage Vc1[first phase-referred signal] provided to 211a and control voltage Vc1[second phase-referred signal] provided to 211b are synchronized based on “clock signal CLK”), and
wherein the amplitude-referred signal is synchronized with respect to the first phase- referred signal and/or the second phase-referred signal (Fig. 1, 4, 5, 0051: all signals, including Vc1 and Vc3 are synchronized to each other based on “clock signal CLK”);
wherein at least the first modulating unit and the second modulating unit are configured to form a phase shifting and/or modulating unit comprising a corresponding phase path (Fig, 1, 4, 5: at least MIXa1 and MIXa2 form a phase shifting and/or modulating unit in corresponding I-phase path and Q-phase path), and/or wherein at least the third modulating unit is configured to form an amplitude modulating unit ((Fig. 1, 4, 5, Para. [0047]: power amplifier 411/ amplitude modulating unit where “the output level [amplitude] is raised and lowered [modulated] by controlling the gain of … the power amplifiers 411…)) comprising a corresponding amplitude path (Fig, 1, 4, 5: baseband circuit (LSI) 300 to power amplifiers411 provides a corresponding amplitude path).
Although Matsui et al. fairly teaches an output of MIXa1 and an output of MIXa2 are combined and provided at an output node as addressed above, they do not teach the such function is performed by:
“an adding unit.”
On the other hand, in the same field of endeavor (Abstract: “A polar transmitter”), Khalaf et al. teaches;
“an adding unit (Fig. 1, 8: the adder unit/ “Input Transformer” in the “I/Q Mixer” that form the sum of an output of I mixer and an output of Q mixer)”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the combining of an output of MIXa1 and an output of MIXa2 and providing its sum at an output node in Matsui et al.’s invention can be implemented using a adder unit as discloses by Khalaf et al., where doing so would (Khalaf et al., I. INTRODUCTION, Section IV. MEASUREMENTS AND ANALYSIS Part. C. Measurement Results ) provide a polar transmitter with “higher efficiency than a conventional implementation with linear PAs” and “reduction in the output power” of the I-Q mixer.
Regarding Claim 2, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 1 above, where Khalaf et al. further teaches;
wherein the digital polar transmitter further comprises:
a driver unit (Fig. 8: “PA 1st stage (pre-PA)”) for providing a driver unit output on the basis of the adding unit output (Fig. 1, 8: “PA 1st stage (pre-PA)” provides a driver unit output to “PA 2nd stage” on the basis of the adding unit/“Input Transformer” output),
wherein the third modulating unit (Fig. 1, 8: “PA 2nd stage”) is configured to amplify the driver unit output and to provide the correspondingly amplified driver unit output at a third modulating unit output (Fig. 1, 8: “PA 2nd stage” amplifies the output of “PA 1st stage (pre-PA)” output and provide the correspondingly amplified driver unit output at a “PAD OUT”/third modulating unit output).
Regarding Claim 4, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 1 above, where Khalaf et al. further teaches;
wherein a delay between the phase path and the amplitude path is compensated preferably on the basis of a delay estimation (Section II. ARCHITECTURE AND SYSTEM TRADEOFFS, Part A. Signal Behavior and System-Level Tradeoffs: “a time-delay mismatch between the amplitude and phase paths, which arises from the difference in signal delay between the circuit blocks in the two signal paths. The minimal time step (i.e., time resolution) required to synchronize the two paths depends on the target EVM. For example, approximately 10 ps resolution is required to synchronize the two paths and realize a target EVM of −30 dB.” That is, a time delay between phase path and the amplitude path are compensated, e.g., on the basis of a delay estimation of 10 ps).
Regarding Claim 10, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 1 above, where Khalaf et al. further teaches;
wherein at least the first modulating unit and the second modulating unit are configured to form a phase shifting and/or modulating unit, preferably a cartesian-based phase shifting and/or modulating unit, comprising a corresponding phase path (Fig. 1, Section II. ARCHITECTURE AND SYSTEM TRADEOFFS, Part A. 60 GHz Polar TX Architecture: “The phase path then reverts to the I-Q signal, and the TX operates in a Cartesian configuration”) , and/or
wherein at least the third modulating unit is configured to form a digital-to-analog converter, preferably a radio frequency digital-to-analog converter, comprising a corresponding amplitude path (Fig. 1, Abstract: “the amplitude path modulates an RF-DAC [digital-to-analog converter -forms the third modulating unit]” ).
Regarding Claim 11, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 2 above, where Khalaf et al. further teaches;
The digital polar transmitter according to claim 2,
wherein a frequency response of the driver unit is equalized (Fig. 8: “Cneut 10fF” capacitors equalize a frequency response of “PA 1st stage (pre-PA)”/the driver unit).
Regarding Claim 12, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 1 above, where Matsui et al. further teaches;
wherein the first modulating unit comprises or is a first variable-gain amplifier (Fig. 1, 4, 5: first modulating unit -211a, LPF1, MIXa1 comprises or is a second variable-gain amplifier 211b), and/or
wherein the second modulating unit comprises or is a second variable-gain amplifier (Fig. 1, 4, 5: second modulating unit - 211b, LPF2, MIXa2 comprises or is a second variable-gain amplifier 211b).
Regarding Claim 13, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 1 above, where Matsui et al. further teaches;
wherein the third modulating unit comprises or is a third variable-gain amplifier (Fig. 1: power amplifier 411/ third modulating unit constitutes a variable-gain amplifier since it varies a gain applied to the amplitude signal. See further evidentiary document, de Vreede (US 20170272037 A1, FIG. 24, Para. [0066]) teaching RF-DAC comprises or is a variable-gain amplifier).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 20040229592 A1) further in view of Khalaf et al. (NPL titled: "Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication," in IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1579-1592, July 2016) further in view of TERTINEK (WO 2018052612 A1 previously cited).
Regarding Claim 5, Matsui et al. in view of Khalaf et al. discloses all as applied to claim 4 above, however they do not teach:
wherein the delay estimation is based on a first signal sequence and/or a second signal sequence extracted from an output signal of the digital polar transmitter preferably for the case that a multisine signal is applied to the digital polar transmitter.
On the other hand, in the same field of endeavor (Abstract: “a polar transmitter”), TERTINEK teaches;
wherein the delay estimation (Abstract, Fig. 1, 2, Para. [0021]: “The estimation circuitry 160 is configured to provide this estimated AMPM delay value [the delay estimation]”) is based on a first signal sequence and/or a second signal sequence extracted from an output signal of the digital polar transmitter preferably for the case that a multisine signal is applied to the digital polar transmitter (Fig. 1, 1A, Para. [0015], [00018]: “extract received data I' [a first signal sequence], Q [a second signal sequence]'” from an output signal of the digital polar transmitter (Fig. 1, Para. [00018]: from “calibration TX signal” in response to a multisine/”Calibration Data Singal”/IQ signal is applied to the digital polar transmitter).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the delay estimation such as time delay estimation in Matsui et al. in view of Khalaf et al.’s invention can be estimated based on the I’ and Q’ signals extracted from the output the digital polar transmitter in responses to in response to a multisine/”Calibration Data Singal”/IQ signal is applied to the digital polar transmitter as taught by TERTINEK where doing so would (TERTINEK, Para. [0013]) provide for “accurate time alignment of the AM signal and the PM LO signal before the signals” decreasing “adjacent channel leakage ratio (ACLR).”
Allowable Subject Matter
Claim 14-16 and 18 are allowed.
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam K Ahn can be reached at 5712723044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633
