DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/22/2024 is in compliance with the provisions of 37 C.F. R 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Oath/Declaration
The Oath/Declaration filed on 06/02/2025 is hereby acknowledged.
Drawings
The drawings are objected to because Figure 2B is illegible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 10 ,12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (US 20090088091 A1) .
Regarding Claim 1, Shen et al. discloses;
A digital polar transmitter (Fig. 3, Para. [0022]: transmitter 300) with improved transmission behavior, comprising:
a first modulating unit, especially a first phase modulating unit (Fig. 3: variable gain amplifier 331), with a first variable gain being controllable with the aid of a first phase-referred signal (Fig. 3, Para. [0029], [0032], [0033]: “the phase of a decomposed signal can be sent to a up-converting modulator for a PLL to up-convert the decomposed signal, and the phase modulated decomposed signal [first phase-referred signal] can then be amplified by a VGA using the amplitude of the decomposed signal”),
a second modulating unit, especially a second phase modulating unit (Fig. 3: variable gain amplifier 33K), with a second variable gain being controllable with the aid of second phase-referred signal (Fig. 3, Para. [0032], [0033]: “the phase of a decomposed signal can be sent to a up-converting modulator for a PLL to up-convert the decomposed signal, and the phase modulated decomposed signal [second phase-referred signal] can then be amplified by a VGA using the amplitude of the decomposed signal”),
a third modulating unit, especially an amplitude modulating unit (Fig. 3, Para. [0029]: a third variable gain amplifier, e.g. 332/32K, among the “K numbers of variable gain amplifiers (VGAs) 331-33K”), with a third variable gain being controllable with the aid of an amplitude-referred signal (Fig. 3, Para. [0034]: “the signal decomposer component 320 can send amplitude information, (e.g., A.sub.i(t) [an amplitude-referred signal] of the i decomposed signal) to a VGA 33i [32i] to amplitude modulate the i-th phase modulated”), and
an adding unit (Fig. 3: a summer 350) for forming the sum of an output of the first modulating unit and an output of the second modulating unit (Fig. 3, Para. [0034]: “the output signals of the VGAs 331-33K can be added with a summer 350.” That is, the outputs 331 and 33K are summed by adder 350) and providing the sum at an adding unit output (Fig. 3, Para. [0030]: “The output terminal 340 [an adding unit output] of the summer 350 can be the output terminal 340 of the transmitter 300”),
wherein the first phase-referred signal and the second phase-referred signal are synchronized (Fig. 4, Para. [0042]: “The signal decomposer component 420 can control the PPLs 491 and 492 to an extent to up-convert the two decomposed signals 411 [first phase-referred signal], 412 [second phase-referred signal] to cos
ω
(t) and cos(
ω
t+
π
).” That is, the 411 [first phase-referred signal], 412 [second phase-referred signal] are synchronized to exactly
π
degrees apart), and
wherein the amplitude-referred signal is synchronized with respect to the first phase-referred signal and/or the second phase-referred signal (Para. [0042]: “The phase and amplitude modulated or up-converted output signals of VGA1 431 and VGA2 432 can be represented by A(t)*[S11SS1]*cos(
ω
t) and A(t)*[0SS00S]*cos(
ω
t+
π
).” That is, amplitude-referred signal, A(t), is synchronized with respect to the first phase-referred signal, cos(ωt), and/or the second phase-referred signal, cos(ωt+ π)).
Regarding Claim 10, Shen et al. discloses;
wherein at least the first modulating unit and the second modulating unit are configured to form a phase shifting and/or modulating unit, preferably a cartesian-based phase shifting and/or modulating unit, comprising a corresponding phase path (Fig. 1, Para. [0025]: “a mixer 130 coupled to a first input terminal 110 for a baseband quadrature signal (Q signal), and a mixer 135 coupled to a second input terminal 115 for a baseband in-phase signal (I signal)”. That is, IQ mixer corresponds to the first modulating unit and the second modulating unit forming a cartesian-based phase shifting and/or modulating unit and a corresponding phase path/phase shift path 120), and/or wherein at least the third modulating unit is configured to form a digital-to-analog converter, preferably a radio frequency digital-to-analog converter, comprising a corresponding amplitude path (optional limitation not addressed).
Regarding Claim 12, Shen et al. discloses;
wherein the first modulating unit comprises or is a first variable-gain amplifier (Fig. 3: first variable gain amplifier 331), and/or wherein the second modulating unit comprises or is a second variable-gain amplifier (Fig. 3: second variable gain amplifier 33K).
Regarding Claim 13, Shen et al. discloses;
wherein the third modulating unit comprises or is a third variable-gain amplifier (Fig. 3, Para. [0029]: third variable gain amplifier, e.g. 332 or 32K, amount the “K numbers of variable gain amplifiers (VGAs) 331-33K”).
Claims 14, 15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TERTINEK (WO 2018052612 A1).
Regarding Claim 14, TERTINEK discloses:
A method for improving the transmission behavior of a digital polar transmitter (Abstract: “Methods…for calibrating a polar transmitter”), the method comprising the steps of:
applying a multisine signal to the digital polar transmitter (Fig. 1, Para. [00011]: “polar transmitter 100 inputs an IQ data point that includes an I component and a Q component”), extracting a first signal sequence and/or a second signal sequence (Fig. 1, Para. [00018]: “extract received data I' [a first signal sequence], Q [a second signal sequence]'”) from an output signal of the digital polar transmitter (Fig. 1, Para. [00018]: from “calibration TX signal”) for a delay estimation (Fig. 1a, Para. [00021]: “estimation circuitry 1 60 is configured to input the result signal extracted by the feedback receiver 120 and estimate the AMPM delay value”), and
compensating a delay between the corresponding phase path of a phase shifting and/or modulating unit, preferably a cartesian-based phase shifting and/or modulating unit (Fig. 1, 1A, 2: “IQ” path including a “IQ DSP”/cartesian-based phase shifting and/or modulating unit), and the corresponding amplitude path of a digital-to-analog converter, preferably a radio frequency digital-to-analog converter, on the basis of the delay estimation (Abstract, Para. [00013]: “generate an adjustment signal that communicates an amplitude modulation/phase modulation (AMPM) delay value to AMPM delay circuitry that is configured to delay, based at least on the AMPM delay value, output of a signal by digital signal processing circuitry (DSP) in the polar transmitter”…“The signal delay through by the AM path is determined by the delay through the AM DSP as well as the mixed signal RFDAC”).
Regarding Claim 15, TERTINEK discloses:
wherein the first signal sequence comprises or is a first part of the output signal of the digital polar transmitter (Fig. 1, 1A, 2, Para. [00018]: “received data I' [ first signal sequence]” is a first part of the calibration TX signal/output signal of the polar transmitter 100 or 200),
wherein in the first part, only the corresponding amplitude is modulating (Fig. 1, 1A, 2, Para. [0003], [00018], [00020]: “The AM path includes circuitry that processes a magnitude component of the polar data sample to generate an amplitude modulation signal”… EQ. 2 – I'(t)…“the adjustable amount of delay that is introduced into the AM path by the AMPM delay circuitry when a particular AMPM delay value is used” ), or
wherein the second signal sequence comprises or is a second part of the output signal of the digital polar transmitter (Fig. 1, 1A, 2, Para. [00018]: “received data Q' [second signal sequence]” is a second part of the calibration TX signal/output signal of the polar transmitter 100 or 200), wherein in the second part only the corresponding phase is modulating (“The PM path includes phase modulator circuitry that processes a frequency or phase component of a polar data sample to generate a phase modulated RF signal”).
Regarding Claim 18, TERTINEK discloses:
A computer program with program code (Para. [00066]: “computer program”) for improving the transmission behavior of a digital polar transmitter stored on a computing device (Fig. 5: User Equipment 500) and executed by a processor (Fig. 5: Processor 502)to:
apply a multisine signal to the digital polar transmitter(Fig. 1, Para. [00011]: “polar transmitter 100 inputs an IQ data point that includes an I component and a Q component”), extracting a first signal sequence and/or a second signal sequence (Fig. 1, Para. [00018]: “extract received data I' [a first signal sequence], Q [a second signal sequence]'”) from an output signal of the digital polar transmitter (Fig. 1, Para. [00018]: from “calibration TX signal”) for a delay estimation (Fig. 1a, Para. [00021]: “estimation circuitry 1 60 is configured to input the result signal extracted by the feedback receiver 120 and estimate the AMPM delay value”), and
compensate a delay between the corresponding phase path of a phase shifting and/or modulating unit, preferably a cartesian-based phase shifting and/or modulating unit (Fig. 1, 1A, 2, Abstract, Para. [00013]: “generate an adjustment signal that communicates an amplitude modulation/phase modulation (AMPM) delay value to AMPM delay circuitry that is configured to delay, based at least on the AMPM delay value, output of a signal by digital signal processing circuitry (DSP) in the polar transmitter” where “IQ” path including a “IQ DSP”/cartesian-based phase shifting and/or modulating unit), and the corresponding amplitude path of a digital-to-analog converter, preferably a radio frequency digital-to-analog converter, on the basis of the delay estimation (Para. [00013]: “The signal delay through by the AM path is determined by the delay through the AM DSP as well as the mixed signal RFDAC”).
Allowable Subject Matter
Claims 2-9, 11, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mehta et al., ("Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter," 2011 IEEE International Symposium on Radio-Frequency Integration Technology, Beijing, China, 2011, pp. 169-172 (Year: 2011)) discloses (Abstract, Conclusions) “mismatch considerations for an RF-DAC designed for a digital polar EDGE transmitter. A new concept of phase mismatch is introduced in the context of a passband RF-DAC operating at multi-GHz frequencies. Its specifications are derived based on the wideband noise (WBN) requirements of the transmitter. Digital predistortion is designed for recompensation of the systematic 1x-4x amplitude mismatch by characterizing the mismatch using an on-chip receiver and storing the distortions in a look-up-table. Additional specifications are derived for tolerable random clock skew in the array of transistors.”
Lin et al., "System-level requirements for implementing wide dynamic range pulse-modulated polar transmitters," 2011 IEEE Radio and Wireless Symposium, Phoenix, AZ, USA, 2011, pp. 319-322 (Year: 2011) discloses (Abstract, Conclusions) “an improved pulse-modulated polar transmitter for wide dynamic range applications is presented. An auxiliary digital gain/attenuation block is added in front of the DPWM block. With proper digital gain/attenuation control, wide dynamic range can be achieved without requiring a wide dynamic range RF VGA block. Moreover, fine tuning of the average output power level can be achieved by using the digital gain/attenuation instead of a controlling the RF VGA. Simulation results show that using the proposed technique, wide dynamic range pulse-modulated polar transmitters can be implemented accurately with ease. An RF VGA with just 32 dB of dynamic range is sufficient to pass the 80 dB power control range of the CDMA2000 standard. Simulation results also show that a DAC with 5-bit resolution for the envelope path and two DACs with 3-bit resolution for the phase path are sufficient to pass the ACPR requirements of the CDMA2000 standard. Compared to a conventional transmitter utilizing linear PAs, the proposed architecture would have lower cost and achieve much higher efficiency.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
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/AMNEET SINGH/Examiner, Art Unit 2633
/SAM K AHN/Supervisory Patent Examiner, Art Unit 2633