DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6-7, 14-15 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 8,013,635) in view of Yeung et al (US 2011/0187438).
For claim 1, Jain teaches a clock buffer circuit (Figure 3), comprising:
a first clock driver (310A1), including two transistors connected in series (335A, 335B), configured to receive a first input clock signal (320, col. 4, lines 38-39) and an enable signal (330) to generate a first output clock signal (325), the two transistors of the first clock driver receiving the first input clock signal and the enable signal, respectively (as understood by examination of Figure 3); and
a second clock driver (310N1), including two transistors connected in series (NMOS within 310N1 which receives 340 at its gate, NMOS within 310N1 which receives 330 at its gate), configured to receive a second input clock signal (340) and the enable signal to generate a second output clock signal (signal at the bottom terminal common to both PMOS transistors within 310N1), the two transistors of the second clock driver receiving the second input clock signal and the enable signal, respectively (as understood by examination of Figure 3).
Jain fails to teach:
wherein a node between the two transistors of the first clock driver and a node between the two transistors of the second clock driver are electrically connected.
However, Yeung teaches power gating with reduced current leakage by “providing two sets of switching devices, one having a higher resistance when closed than the other. The higher resistance devices impede current leakage and help reduce power consumption, however, they also reduce the performance of the circuit. Thus, one set of switching devices can be closed when a high performance mode of operation is required, while the other set can be closed when a lower performance mode is acceptable. In this way power consumption can be reduced without powering the circuit down. Furthermore, the switch back to high performance operation from the low performance mode can be made more quickly and without the same inrush current problem as occurs when switching from inactive to high performance mode” [8].
Yeung’s Figure 3 teaches a plurality of logic circuits (42, 44) connected to a first set of transistors having a low threshold voltage (14) controlled by control signal A and a second set of transistors having a high threshold voltage (16) controlled by control signal B.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add a virtual VSS line to Jain’s circuit (Figure 3) such that Yeung’s plurality of transistors 14 and 16 are connected between Jain’s 335 and ground in order to reduce power consumption.
Furthermore, all the elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one skilled in the art at the time of the invention.
The combination of Jain and Yeung as cited above teaches a clock buffer circuit, comprising:
a first clock driver (310A1 of Jain, a first transistor 14 of Yeung), including two transistors connected in series (335A of Jain, the first transistor 14 of Yeung), configured to receive a first input clock signal (320, col. 4, lines 38-39) and an enable signal (Ctrl_A) to generate a first output clock signal (325), the two transistors of the first clock driver receiving the first input clock signal and the enable signal, respectively (as understood by the combination of references); and
a second clock driver (310N1), including two transistors connected in series (NMOS within 310N1 which receives 340 at its gate, a second transistor 14 of Yeung), configured to receive a second input clock signal (340) and the enable signal to generate a second output clock signal (signal at the bottom terminal common to both PMOS transistors within 310N1), the two transistors of the second clock driver receiving the second input clock signal and the enable signal, respectively (as understood by examination of Figure 3);
wherein a node between the two transistors of the first clock driver and a node between the two transistors of the second clock driver are electrically connected (node directly connected to the top terminals of the first transistor 14 and the second transistor 14, as understood by combination of the references).
For claim 2, Jain in view of Yeung teaches the limitations of claim 1 as cited above and Jain further teaches:
the two transistors of the first clock driver and the two transistors of the second clock driver are each NMOS transistors (as understood by the combination of references).
For claim 3, Jain in view of Yeung teaches the limitations of claim 1 as cited above and Jain further teaches:
the two transistors of the first clock driver are electrically connected between another transistor of the first clock driver (315A) and a voltage terminal to which a ground voltage is supplied (as understood by the combination of references as applied above), and wherein the two transistors of the second clock driver are electrically connected between another transistor of the second clock driver (PMOS receiving 340) and the voltage terminal to which the ground voltage is supplied (as understood by the combination of references as applied above).
For claim 6, Jain teaches a clock buffer circuit, comprising:
a first clock driver (310A1) configured to receive a first input clock signal (320, col. 4, lines 38-39) and an enable signal (330) to generate a first output clock signal (325), the first clock driver including a first virtual ground node (node between 335A and 335B); and
a second clock driver (310N1) configured to receive a second input clock signal (340) and the enable signal to generate a second output clock signal (signal at the bottom terminal common to both PMOS transistors within 310N1), the second clock driver including a second virtual ground node (node between the NMOS transistors within 310N1).
Jain fails to teach:
wherein the first virtual ground node is electrically connected to the second virtual ground node.
However, Yeung teaches power gating with reduced current leakage by “providing two sets of switching devices, one having a higher resistance when closed than the other. The higher resistance devices impede current leakage and help reduce power consumption, however, they also reduce the performance of the circuit. Thus, one set of switching devices can be closed when a high performance mode of operation is required, while the other set can be closed when a lower performance mode is acceptable. In this way power consumption can be reduced without powering the circuit down. Furthermore, the switch back to high performance operation from the low performance mode can be made more quickly and without the same inrush current problem as occurs when switching from inactive to high performance mode” [8].
Yeung’s Figure 3 teaches a plurality of logic circuits (42, 44) connected to a first set of transistors having a low threshold voltage (14) controlled by control signal A and a second set of transistors having a high threshold voltage (16) controlled by control signal B.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add a virtual VSS line to Jain’s circuit (Figure 3) such that Yeung’s plurality of transistors 14 and 16 are connected between Jain’s 335 and ground in order to reduce power consumption.
Furthermore, all the elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one skilled in the art at the time of the invention.
The combination of Jain and Yeung as cited above teaches:
a clock buffer circuit, comprising:
a first clock driver (310A1, a first transistor 14) configured to receive a first input clock signal (320, col. 4, lines 38-39) and an enable signal (CtrlA) to generate a first output clock signal (325), the first clock driver including a first virtual ground node (top terminal of the first transistor 14); and
a second clock driver (310N1, a second transistor 14) configured to receive a second input clock signal (340) and the enable signal to generate a second output clock signal (signal at the bottom terminal common to both PMOS transistors within 310N1), the second clock driver including a second virtual ground node (top terminal of the first transistor 14),
wherein the first virtual ground node is electrically connected to the second virtual ground node (as understood by the combination of references).
For claim 7, Jain in view of Yeung teaches the limitations of claim 6 as cited above and Jain further teaches:
the first and second clock drivers are each a NAND gate (as understood by examination of Figure 3).
For claim 14, Jain teaches a semiconductor apparatus (Figure 3), comprising:
a first clock driver (305A) configured to receive a first input clock signal (320 or 420) and an enable signal (330) to generate a first output clock signal (output of 310A2), the first clock driver including a first virtual node (top terminal of 335B);
a second clock driver (305N) configured to receive a second input clock signal (340) and the enable signal to generate a second output clock signal (output of 310N2), the second clock driver including a second virtual node (node between NMOS transistors within 310N1);
a first data receiver (210, Figure 2) configured to receive a data signal in synchronization with the first output clock signal to generate a first internal data signal (as understood by examination of Figures 2-3 and col. 2, line 50- col. 3 line 41); and
a second data receiver (215, Figure 2) configured to receive the data signal in synchronization with the second output clock signal to generate a second internal data signal (as understood by examination of Figures 2-3 and col. 2, line 50- col. 3 line 41).
Jain fails to teach:
the second virtual node electrically connected to the first virtual node.
However, Yeung teaches power gating with reduced current leakage by “providing two sets of switching devices, one having a higher resistance when closed than the other. The higher resistance devices impede current leakage and help reduce power consumption, however, they also reduce the performance of the circuit. Thus, one set of switching devices can be closed when a high performance mode of operation is required, while the other set can be closed when a lower performance mode is acceptable. In this way power consumption can be reduced without powering the circuit down. Furthermore, the switch back to high performance operation from the low performance mode can be made more quickly and without the same inrush current problem as occurs when switching from inactive to high performance mode” [8].
Yeung’s Figure 3 teaches a plurality of logic circuits (42, 44) connected to a first set of transistors having a low threshold voltage (14) controlled by control signal A and a second set of transistors having a high threshold voltage (16) controlled by control signal B.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add a virtual VSS line to Jain’s circuit (Figure 3) such that Yeung’s plurality of transistors 14 and 16 are connected between Jain’s 335 and ground in order to reduce power consumption.
Furthermore, all the elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one skilled in the art at the time of the invention.
The combination of Jain and Yeung as cited above teaches:
a first clock driver (305A, a first transistor 14) configured to receive a first input clock signal (320) and an enable signal (Ctrl_A) a first output clock signal (output of 310A2), the first clock driver including a first virtual node (node between 335B and the first transistor 14); and
a second clock driver (305N, a second transistor 14) configured to receive a second input clock signal (340) and the enable signal to generate a second output clock signal (output of 310N2), the second clock driver including a second virtual node (node between NMOS transistors within 310N1);
wherein the first virtual node is electrically connected to the second virtual node (as understood by the combination of references).
For claim 15, Jain in view of Yeung teaches the limitations of claim 14 as cited above and Jain further teaches:
the first and second clock drivers are each a NAND gate, and wherein the first and second virtual nodes are each a virtual ground node (as understood by examination of Figure 3).
For claim 17, Jain in view of Yeung teaches the limitations of claim 14 as cited above and Jain further teaches:
the first clock driver comprises two transistors connected in series (335A, a first transistor 14), receiving the first input clock signal and the enable signal, respectively (as understood by the combination of references), and wherein the first virtual node is a node between the two transistors (as understood by the combination of references).
For claim 18, Jain in view of Yeung teaches the limitations of claim 14 as cited above and Jain further teaches:
the second clock driver comprises two transistors connected in series (NMOS within 310N1 that receives 340, a second transistor 14), receiving the second input clock signal and the enable signal, respectively (as understood by the combination of references), and wherein the second virtual node is a node between the two transistors (as understood by the combination of references).
Claim(s) 4-5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 8,013,635) in view of Yeung et al (US 2011/0187438) and official notice.
For claim 4, Jain in view of Yeung teaches the limitations of claim 1 as cited above but fails to teach PMOS transistors as claimed.
However, examiner takes official notice that one having ordinary skill would understand how to substitute PMOS transistors for NMOS transistors within a circuit and vice versa to such that an equivalent function is performed.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to substitute PMOS transistors for all the NMOS transistors of the combination circuit of Jain and Yeung and substitute NMOS transistors for all the PMOS transistors of the combination circuit of Jain and Yeung since the particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
For claim 5, Jain in view of Yeung and official notice teaches the limitations of claim 4 as cited above and Jain further teaches:
the two transistors of the first clock driver are electrically connected between a voltage terminal to which a power supply voltage is supplied (VDD) and another transistor of the first clock driver (as understood by the combination of references), and wherein the two transistors of the second clock driver are electrically connected between the voltage terminal to which the power supply voltage is supplied and another transistor of the second clock driver (as understood by the combination of references).
For claim 19, Jain in view of Yeung teaches the limitations of claim 14 as cited above but fails to teach comparing a data signal with a reference voltage as claimed.
It is noted that Jain teaches that the circuits are ICs and SoCs which are well-known to comprise input data buffers wherein a data signal is compared to a reference voltage.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to use a data buffer at the input of Jain’s 210, 215 and 220 in order to improve signal integrity.
Claim(s) 10-11, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al (US 8,013,635) in view of Van Winkelhoff et al (US 2012/0299636).
For claim 10, Jain teaches a clock buffer circuit (Figure 4), comprising:
a first clock driver (410A1) configured to receive a first input clock signal (420) and an enable signal (435) to generate a first output clock signal (425), the first clock driver including a first virtual supply node (node between 430A and 430B); and
a second clock driver (410N1) configured to receive a second input clock signal (440) and the enable signal to generate a second output clock signal (signal at the bottom terminal of both NMOS transistors within 410N1), the second clock driver including a second virtual supply node (node between PMOS transistors within 410N1).
Jain fails to teach:
wherein the first virtual supply node is electrically connected to the second virtual supply node.
However, Van Winkelhoff teaches power gating having a virtual VDD line which provides a reduced slew rate (Abstract, Figure 1).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add a virtual VDD line to Jain’s apparatus (Figure 3) in order to reduce the slew rate of the gate drive voltage such that the current passing between the power gate supply conductor and Jain’s circuit through the power gating transistor is less than the saturation current of the power gating transistor (Abstract).
Furthermore, all the elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one skilled in the art at the time of the invention.
The combination of Jain and Van Winkelhoff as cited above teaches:
a first clock driver (410A1 of Jain, a first 14 of Van Winkelhoff) configured to receive a first input clock signal (420, Jain) and an enable signal (24, Van Winkelhoff) to generate a first output clock signal (425), the first clock driver including a first virtual supply node (DVDD, Van Winkelhoff); and
a second clock driver (410N1 of Jain, a second 14 of Van Winkelhoff) configured to receive a second input clock signal (440) and the enable signal to generate a second output clock signal (signal at the bottom terminal of both NMOS transistors within 410N1), the second clock driver including a second virtual supply node (DVDD), wherein the first virtual supply node is electrically connected to the second virtual supply node (as understood by the combination of references).
For claim 11, Jain in view of Van Winkelhoff teaches the limitations of claim 10 as cited above and Jain further teaches:
the first and second clock drivers are each a NOR gate (as understood by examination of Figure 4).
For claim 14, Jain teaches a semiconductor apparatus (Figure 4), comprising:
a first clock driver (405A) configured to receive a first input clock signal (420) and an enable signal (435) to generate a first output clock signal (output of 410A2), the first clock driver including a first virtual node (top terminal of 430B);
a second clock driver (405N) configured to receive a second input clock signal (440) and the enable signal to generate a second output clock signal (output of 410N2), the second clock driver including a second virtual node (node between PMOS transistor within 410N1);
a first data receiver (210, Figure 2) configured to receive a data signal in synchronization with the first output clock signal to generate a first internal data signal (as understood by examination of Figures 2-4 and col. 2, line 50- col. 3 line 41); and
a second data receiver (215, Figure 2) configured to receive the data signal in synchronization with the second output clock signal to generate a second internal data signal (as understood by examination of Figures 2-4 and col. 2, line 50- col. 3 line 41).
Jain fails to teach:
the second virtual node electrically connected to the first virtual node.
However, Van Winkelhoff teaches power gating having a virtual VDD line which provides a reduced slew rate (Abstract, Figure 1).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to add a virtual VDD line to Jain’s apparatus (Figure 3) in order to reduce the slew rate of the gate drive voltage such that the current passing between the power gate supply conductor and Jain’s circuit through the power gating transistor is less than the saturation current of the power gating transistor (Abstract).
Furthermore, all the elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one skilled in the art at the time of the invention.
The combination of Jain and Van Winkelhoff as cited above teaches:
a first clock driver (410A1 of Jain, a first 14 of Van Winkelhoff) configured to receive a first input clock signal (420, Jain) and an enable signal (24, Van Winkelhoff) to generate a first output clock signal (425), the first clock driver including a first virtual supply node (DVDD, Van Winkelhoff); and
a second clock driver (410N1 of Jain, a second 14 of Van Winkelhoff) configured to receive a second input clock signal (440) and the enable signal to generate a second output clock signal (signal at the bottom terminal of both NMOS transistors within 410N1), the second clock driver including a second virtual supply node (DVDD), wherein the first virtual supply node is electrically connected to the second virtual supply node (as understood by the combination of references).
For claim 16, Jain in view of Yeung and Van Winkelhoff teaches the limitations of claim 14 as cited above and Jain further teaches:
the first and second clock drivers are each a NOR gate (as understood by examination of Figure 4), and wherein the first and second virtual nodes are each a virtual supply node (as understood from the rejection of claim 14 above).
Allowable Subject Matter
Claims 8-9 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Specifically, the prior art fails to teach the interconnections to the first output node and the second output node as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849