DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao (US 2022/0206695).
In regards to claim 1, Zhao teaches a storage device, comprising:
a storage controller (external memory controller 105, figure 1) including a plurality of first data pins (host pins 365-a, figure 3), the storage controller configured to send a command through a command/address (CA) line (“The CA channels 186 may be configured to communicate commands between the external memory controller 105 and the memory device 110 including control information associated with the commands (e.g., address information).”, paragraph 0042), the command including a first data pattern (“At 620, the memory device 310-d may read mode register values, or some other values stored at or received by the memory device 310-d, where the values may be configured for a channel mapping operation. … In some examples, the mode register values may be based at least in part on signaling received at the memory device 310-d. For example, at 615, the host device 350-d may issue one or more mode register write commands, and the operations of 620 may be based at least in part on the memory device 310-d receiving the mode register write commands.”, paragraph 0119); and
a memory device (memory device 110, figure 1) including a plurality of second data pins (memory pins 325-a, figure 3) connected to the plurality of first data pins through a plurality of data lines (See figure 3),
wherein the memory device is configured to:
receive, from the storage controller, the command including the first data pattern (“At 620, the memory device 310-d may read mode register values, or some other values stored at or received by the memory device 310-d, where the values may be configured for a channel mapping operation. … In some examples, the mode register values may be based at least in part on signaling received at the memory device 310-d. For example, at 615, the host device 350-d may issue one or more mode register write commands, and the operations of 620 may be based at least in part on the memory device 310-d receiving the mode register write commands.”, paragraph 0119), and
generate a second data pattern based on the first data pattern included in the command (“In some examples, the host device 350-d may configure a signaling pattern (e.g., for signaling of 630) through a write mode register (e.g., as part of a set of instructions stored at the host device 350-d).”, paragraph 0120), and
send the second data pattern to the storage controller through the plurality of data lines (“At 630, the memory device 310-d may transmit channel mapping operation signaling based at least in part on the mode register values, or other values. For example, the memory device 310-d may transmit bit sequences, such as those described with reference to Tables 1 and 2, or otherwise convey signaling or pin activations such as those described with reference to FIG. 4B or 5B.”, paragraph 0121), and
wherein the storage controller configured to:
receive a third data pattern in response to the memory device sending the second data pattern (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123),
determine the second data pattern based on the command (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123), and
determine a connection structure between the plurality of first data pins and the plurality of second data pins by comparing the second data pattern generated at the storage controller and the third data pattern received at the storage controller (“At 640, the host device 350-d may determine a channel mapping based at least in part on the channel mapping operation signaling. For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions). In some examples, the channel mapping determined at 640 may include a rerouting of signal paths (e.g., by a multiplexer, by a transistor network). In some examples, the host device 350-d (e.g., an SoC controller) may remap channel pins (e.g., DQ pins) in software or other processing of the host device 350-d.”, paragraph 0123).
In regards to claim 11, Zhao further teaches that the plurality of second data pins of the memory device are in a same order as the plurality of first data pins of the storage controller (“In some examples, communications with a memory device 310 according to this configuration may be supported by a default or initial mapping between data pins 385-c and the host pins 365-c (e.g., a default or initial mapping between data pins 385-c and the memory pins 325-c, a first mapping used by the host device 350-c prior to performing channel mapping operations), such as the dotted line mapping of the pin mapper 380-c shown in FIG. 5A.”, paragraph 0105), or in a reverse order from the plurality of first data pins of the storage controller, and
the second data pattern includes a same number of bits as a number of the plurality of data lines (Table 1 shows bits for DQ0-DQ15).
In regards to claim 16, Zhao further teaches that the storage controller is connected to each of a plurality of memory devices comprising the memory device (“The system 100 may include one or more memory devices, but for ease of description the one or more memory devices may be described as a single memory device 110.”, paragraph 0020).
In regards to claim 17, Zhao further teaches that each of the plurality of memory devices is selectively connected to a channel (“The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description the one or more memory devices may be described as a single memory device 110.”, paragraph 0020), the channel including the command/address line (“In some cases, the channels 115 may include one or more command and address (CA) channels 186.”, paragraph 0042) and the plurality of data lines to communicate with the storage controller (“In some cases, the channels 115 may include one or more data channels 190 (e.g., DQ channels). The data channels 190 may be configured to communicate data and/or control information between the external memory controller 105 and the memory device 110.”, paragraph 0044).
In regards to claim 18, Zhao teaches a storage controller, comprising:
a plurality of first data pins (host pins 365-a, figure 3);
processing circuitry configured to generate a first data pattern (“At 620, the memory device 310-d may read mode register values, or some other values stored at or received by the memory device 310-d, where the values may be configured for a channel mapping operation. … In some examples, the mode register values may be based at least in part on signaling received at the memory device 310-d. For example, at 615, the host device 350-d may issue one or more mode register write commands, and the operations of 620 may be based at least in part on the memory device 310-d receiving the mode register write commands.”, paragraph 0119); and
a logic circuit configured to,
send a command including the generated first data pattern to a memory device (“In some examples, the mode register values may be based at least in part on signaling received at the memory device 310-d. For example, at 615, the host device 350-d may issue one or more mode register write commands, and the operations of 620 may be based at least in part on the memory device 310-d receiving the mode register write commands.”, paragraph 0119) through a command/address line (“In some examples, the signaling of 615 may be conveyed over a CA bus, which may include signaling via memory pins 335 or host pins 375 (e.g., pins separate from those conveying signaling of 630 for mapping of the subject channel) described with reference to FIG. 3.”, paragraph 0120), wherein the memory device is configured to generate a second data pattern based on the first data pattern included in the command (“In some examples, the host device 350-d may configure a signaling pattern (e.g., for signaling of 630) through a write mode register (e.g., as part of a set of instructions stored at the host device 350-d).”, paragraph 0120);
receive, in response to the memory device sending the second data pattern through a plurality of data lines, a third data pattern, the second data pattern generated based on the command (“At 630, the memory device 310-d may transmit channel mapping operation signaling based at least in part on the mode register values, or other values. For example, the memory device 310-d may transmit bit sequences, such as those described with reference to Tables 1 and 2, or otherwise convey signaling or pin activations such as those described with reference to FIG. 4B or 5B.”, paragraph 0121; “For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123);
determine the second data pattern based on the command (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123); and
determine, based on the second data pattern and the third data pattern, a connection structure between the plurality of first data pins and a plurality of second data pins of the memory device (“At 640, the host device 350-d may determine a channel mapping based at least in part on the channel mapping operation signaling. For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions). In some examples, the channel mapping determined at 640 may include a rerouting of signal paths (e.g., by a multiplexer, by a transistor network). In some examples, the host device 350-d (e.g., an SoC controller) may remap channel pins (e.g., DQ pins) in software or other processing of the host device 350-d.”, paragraph 0123), the plurality of first data pins being connected to the plurality of second data pins through the plurality of data lines (See figure 3).
In regards to claim 20, Zhao teaches a method of operating a storage device including a storage controller and a memory device, the method comprising:
sending, by the storage controller, a command including a first data pattern (“At 620, the memory device 310-d may read mode register values, or some other values stored at or received by the memory device 310-d, where the values may be configured for a channel mapping operation. … In some examples, the mode register values may be based at least in part on signaling received at the memory device 310-d. For example, at 615, the host device 350-d may issue one or more mode register write commands, and the operations of 620 may be based at least in part on the memory device 310-d receiving the mode register write commands.”, paragraph 0119), through a command/address line (“In some examples, the signaling of 615 may be conveyed over a CA bus, which may include signaling via memory pins 335 or host pins 375 (e.g., pins separate from those conveying signaling of 630 for mapping of the subject channel) described with reference to FIG. 3.”, paragraph 0120);
generating, by the memory device, in response to receiving the command from the storage controller, a second data pattern corresponding to the first data pattern based on the command (“At 620, the memory device 310-d may read mode register values, or some other values stored at or received by the memory device 310-d, where the values may be configured for a channel mapping operation. … In some examples, the mode register values may be based at least in part on signaling received at the memory device 310-d. For example, at 615, the host device 350-d may issue one or more mode register write commands, and the operations of 620 may be based at least in part on the memory device 310-d receiving the mode register write commands.”, paragraph 0119; “In some examples, the host device 350-d may configure a signaling pattern (e.g., for signaling of 630) through a write mode register (e.g., as part of a set of instructions stored at the host device 350-d).”, paragraph 0120);
sending, by the memory device, the second data pattern to the storage controller through a plurality of data lines (“At 630, the memory device 310-d may transmit channel mapping operation signaling based at least in part on the mode register values, or other values. For example, the memory device 310-d may transmit bit sequences, such as those described with reference to Tables 1 and 2, or otherwise convey signaling or pin activations such as those described with reference to FIG. 4B or 5B.”, paragraph 0121);
receiving, by the storage controller, in response to the memory device sending the second data pattern, a third data pattern (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123);
determining, by the storage controller, the second data pattern based on the command (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123); and
determining, by the storage controller, based on the second data pattern and the third data pattern, a connection structure between a plurality of first data pins of the storage controller and a plurality of second data pins of the memory device (“At 640, the host device 350-d may determine a channel mapping based at least in part on the channel mapping operation signaling. For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions). In some examples, the channel mapping determined at 640 may include a rerouting of signal paths (e.g., by a multiplexer, by a transistor network). In some examples, the host device 350-d (e.g., an SoC controller) may remap channel pins (e.g., DQ pins) in software or other processing of the host device 350-d.”, paragraph 0123), the plurality of first data pins and the plurality of second data pins being connected to each other through the plurality of data lines (See figure 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-8, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US 2022/0206695) in view of Park et al. (US 2022/0101893).
In regards to claim 2, Zhao further teaches that the storage controller is further configured to control, based on the second data pattern and the third data pattern, a circuit connected to the plurality of data lines (“At 650, the memory device 310-d and the host device 350-d may communicate information based at least in part on the mapping determined at 640. For example, the host device 350-d may receive signaling over a set of pins and map or route the signaling according to the determined mapping. In one example, the host device 350-d may map signaling received over a set of host pins 365 (e.g., related to a read operation), and route the received signaling to different data pins 385 prior to conveying related signaling to another portion of the host device 350-d (e.g., to an external memory controller 105). In another example, the host device 350-d may map signaling received over a set of data pins 385 (e.g., at a pin mapper 380, related to a write operation), and route the received signaling to different host pins 365 prior to conveying related signaling to the memory device 310-d.”, paragraph 0124), and
the circuit is configured to change, based on controlling the circuit, a signal arrangement of data input to the circuit (“In some examples, the pin mapper 380-a may refer to a configurable switching network (e.g., a transistor network, a multiplexer) that routes, couples, or connects a physical signal path associated with one of the host pins 365-a with a physical signal path associated with one of the data pins 385-a.”, paragraph 0080).
Zhao fails to teach that the circuit is a swap circuit, wherein
the storage controller is further configured to determine to activate the swap circuit.
Park teaches that the circuit is a swap circuit (swap circuit 400, figure 5), wherein
the storage controller is further configured to determine to activate the swap circuit (“The swap decision circuit 410 may receive the first to eighth data signals DQ[0] to DQ[7], such as via a multiplexed and/or multi-conductor bridge, generate a swap enable signal SE, and output the swap enable signal SE to the plurality of multiplexers 420. The swap enable signal SE may serve as a selection signal for each of the multiplexers 420.”, paragraph 0064).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhao with Park such that the circuit is a swap circuit, wherein
the storage controller is further configured to determine to activate the swap circuit
in order to easily support a mirrored mounting.
In regards to claim 3, Zhao further teaches that the storage controller is further configured to:
control the circuit by comparing an arrangement of the determined second data pattern with an arrangement of the third data pattern (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions). In some examples, the channel mapping determined at 640 may include a rerouting of signal paths (e.g., by a multiplexer, by a transistor network).”, paragraph 0123).
In regards to claim 4, Park further teaches that the storage controller is further configured to deactivate the swap circuit (“when the swap address ADDR_SWAP corresponds to a signal to turn OFF the swap mode of the memory chip 2000, the swap decision circuit may determine the logic level of the swap enable signal SE to be logic low”, paragraph 0097).
Zhao further teaches that the second data pattern being a same as the third data pattern (“In some examples, communications with a memory device 310 according to this configuration may be supported by a default or initial mapping between data pins 385-c and the host pins 365-c (e.g., a default or initial mapping between data pins 385-c and the memory pins 325-c, a first mapping used by the host device 350-c prior to performing channel mapping operations), such as the dotted line mapping of the pin mapper 380-c shown in FIG. 5A.”, paragraph 0105).
In regards to claim 5, Park further teaches that the storage controller is further configured to send a swap enable signal to the swap circuit for activating the swap circuit (“As an example, when the swap address indicates a swap mode ON state of the memory chip 2000, the swap decision circuit 410 may output the swap enable signal SE of a first logic level (e.g., logic high).”, paragraph 0069).
Zhao further teaches the second data pattern and the third data pattern being different (“If the host device 350-d does not successfully determine a channel mapping at 640, the host device 350-d may repeat one or more of the preceding steps to support a successful determination or confirmation.”, paragraph 0123).
In regards to claim 6, Park further teaches that the swap circuit comprises a plurality of multiplexers (“Referring to FIG. 5, the swap circuit 400 may include a swap decision circuit 410 and a plurality of multiplexers 420.”, paragraph 0063),
each of the plurality of multiplexers are connected to the plurality of data lines (“Each of the plurality of multiplexers 420 may receive two signals of the first to eighth data signals DQ[0] to DQ[7]”, paragraph 0070), and
the storage controller is further configured to send to the plurality of multiplexers, a selection signal for selecting a data line to be connected to each of the plurality of multiplexers from among the plurality of data lines (“select as output either one of the two signals according to the swap enable signal SE output by the swap decision circuit 410”, paragraph 0070).
Zhao further teaches the second data pattern and the third data pattern being different (“If the host device 350-d does not successfully determine a channel mapping at 640, the host device 350-d may repeat one or more of the preceding steps to support a successful determination or confirmation.”, paragraph 0123).
In regards to claim 7, Zhao further teaches that the storage controller comprises the circuit (pin mapper 380-a, figure 3),
the circuit is further configured to
receive first data to be sent to the memory device, the first data including a first arrangement of data signals (data pins 385-a, figure 3), and
output second data to the plurality of first data pins, the second data including a second arrangement of data signals changed from the first arrangement of data signals included in the first data (paragraph 0080),
the memory device is configured to receive third data through the plurality of data lines, the third data including a third arrangement of data signals changed from the second arrangement of data signals included in the second data (“For example, as shown in FIG. 4B, to indicate a memory pin 325-b or host pin 365-b corresponding to the information position D4, the memory device 310-b may activate or transmit signaling of a logic state for the information position D4 via the memory pin 325-b-7, which is coupled with the host pin 365-b-7. Although the default or initial mapping of FIG. 4A would have mapped the host pin 365-b-7 with the data pin 385-b-7, the host device 350-b may be configured to interpret the signaling of FIG. 4B as corresponding to the information position D4, which should correspond to the data pin 385-b-5. Thus, as shown in FIG. 4B, the host device 350-b (e.g., the pin mapper 380-b) may determine a mapping between the host pin 365-b-7 and the data pin 385-b-5, shown by the dotted line within the pin mapper 380-b, based at least in part on the signaling received via the memory pin 325-b-7 and the host pin 365-b-7.”, paragraph 0091), and
the third data is a same as the first data (See figure 4C).
In regards to claim 8, Zhao further teaches that the storage controller comprises the circuit (pin mapper 380-a, figure 3),
the storage controller is further configured to receive, through the plurality of data lines, second data with an arrangement of data signals changed from an arrangement of data signals included in first data to be sent from the memory device to the storage controller (“The system 100 may thus be configured to communicate information (e.g., information of a read command from a memory device 110 to a host device, information of a write command from a host device to a memory device 110) via the data channel based at least in part on the determined mapping (e.g., a dynamic mapping, based on the particular coupling between the memory device 110 and the host device).”, paragraph 0055),
the circuit is further configured to receive the second data, and output third data with an arrangement of data signals changed from the arrangement of data signals included in the second data (“In some examples, the memory device may be configured to transmit or receive the signaling of 650 (e.g., for a read command) based at least in part on having transmitted the channel mapping operation signaling 630, or otherwise determining that a channel mapping operation has been performed, or that the channel mapping of 640 has been determined.”, paragraph 0124), and
the third data is a same as the first data (See figure 4C).
In regards to claim 10, Park further teaches that the memory device comprises the swap circuit (“Referring to FIG. 4, the interface circuit 2100 may be included in the plurality of chips 2000 of FIG. 1. For convenience of explanation, it is assumed that each of the plurality of chips 2000 is a memory chip. The interface circuit 2100 may include a plurality of input/output pins 100, a plurality of buffers 200, a plurality of samplers 300, and a swap circuit 400.”, paragraph 0058),
the memory device is configured to receive, through the plurality of data lines, second data with an arrangement of data signals changed from an arrangement of data signals included in first data to be sent from the storage controller to the memory device (“When 8-bit signals DQ[0] to DQ[7] passing through the plurality of samplers 300 are input to the swap circuit 400, the swap circuit 400 may output the data signals DQ[0] to DQ[7] as they are or swap and output the data signals DQ[7] to DQ[0] according to the swap mode.”, paragraph 0060; “However, because the first semiconductor chip 21 and the second semiconductor chip 22 may be connected to each other using the mirror method, the input/output pins of the first semiconductor chip 21 and the input/output pins of the second semiconductor chip 22 may be swapped when actively connected to each other.”, paragraph 0051),
the swap circuit is further configured to receive the second data, and output third data with an arrangement of data signals changed from the arrangement of data signals included in the second data (“When 8-bit signals DQ[0] to DQ[7] passing through the plurality of samplers 300 are input to the swap circuit 400, the swap circuit 400 may output the data signals DQ[0] to DQ[7] as they are or swap and output the data signals DQ[7] to DQ[0] according to the swap mode.”, paragraph 0060), and
the third data is a same as the first data (“The present disclosure provides a memory chip that identifies whether a connected chip is set to a correct swap mode based on a command and an address without allocating a separate pin, and controls a swap mode of the chip based on results of identification.”, paragraph 0005).
In regards to claim 19, Zhao further teaches that the logic circuit is configured to control a circuit connected to the plurality of data lines (“At 650, the memory device 310-d and the host device 350-d may communicate information based at least in part on the mapping determined at 640. For example, the host device 350-d may receive signaling over a set of pins and map or route the signaling according to the determined mapping. In one example, the host device 350-d may map signaling received over a set of host pins 365 (e.g., related to a read operation), and route the received signaling to different data pins 385 prior to conveying related signaling to another portion of the host device 350-d (e.g., to an external memory controller 105). In another example, the host device 350-d may map signaling received over a set of data pins 385 (e.g., at a pin mapper 380, related to a write operation), and route the received signaling to different host pins 365 prior to conveying related signaling to the memory device 310-d.”, paragraph 0124) by comparing an arrangement of the determined second data pattern and an arrangement of the third data pattern (“At 640, the host device 350-d may determine a channel mapping based at least in part on the channel mapping operation signaling. For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123).
Zhao fails to teach that the logic circuit is further configured to determine to activate a swap circuit. Park teaches that the logic circuit is further configured to determine to activate a swap circuit (“The swap decision circuit 410 may receive the first to eighth data signals DQ[0] to DQ[7], such as via a multiplexed and/or multi-conductor bridge, generate a swap enable signal SE, and output the swap enable signal SE to the plurality of multiplexers 420. The swap enable signal SE may serve as a selection signal for each of the multiplexers 420.”, paragraph 0064). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhao with Park such that the logic circuit is further configured to determine to activate a swap circuit in order to easily support a mirrored mounting.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US 2022/0206695) in view of Park et al. (US 2022/0101893) and Ayyapureddi et al. (US 2024/0311231).
In regards to claim 9, Park further teaches that the memory device comprises the swap circuit (“Referring to FIG. 4, the interface circuit 2100 may be included in the plurality of chips 2000 of FIG. 1. For convenience of explanation, it is assumed that each of the plurality of chips 2000 is a memory chip. The interface circuit 2100 may include a plurality of input/output pins 100, a plurality of buffers 200, a plurality of samplers 300, and a swap circuit 400.”, paragraph 0058),
the swap circuit is further configured to
receive first data, the first data including a first arrangement of data signals (“Each of the plurality of multiplexers 420 may receive two signals of the first to eighth data signals DQ[0] to DQ[7], and select as output either one of the two signals according to the swap enable signal SE output by the swap decision circuit 410.”, paragraph 0070), and
output second data, the second data including a second arrangement of data signals changed from the first arrangement of data signals included in the first data (paragraph 0072),
the storage controller is further configured to receive third data through the plurality of data lines (“In a data (DATA) output operation of the memory device 9000, the memory interface circuitry 9100 may receive the read enable signal nRE, which toggles through the fifth pin P15, before outputting the data DATA.”, paragraph 0171), and
the third data is a same as the first data (“The present disclosure provides a memory chip that identifies whether a connected chip is set to a correct swap mode based on a command and an address without allocating a separate pin, and controls a swap mode of the chip based on results of identification.”, paragraph 0005).
Zhao further teaches the third data including a third arrangement of data signals changed from the second arrangement of data signals included in the second data (“Regardless of the conceptualization or physical implementation, from the perspective of the host device 350-b, the information positions from top to bottom (e.g., at the data lines 385-b) may not be arranged in a sequential order when the pin mapper 380-b is configured according to the default or initial mapping of FIG. 4A. Rather, as shown, information positions D4 and D6 may be swapped, which may be referred to as swapped pins, swapped information positions, swapped bits, swapped lines, or other descriptions.”, paragraph 0089).
Zhao in view of Park fails to teach the first data to be sent from the memory device to the storage controller; and
output second data to the plurality of second data pins.
Ayyapureddi teaches the first data to be sent from the memory device to the storage controller (“The method 600 may include receiving, via a first sub-wordline (SWL) driver of a memory package, first data from a memory cell array of the memory package, at 610. The method 600 may further include receiving, via a second SWL driver, second data from a memory cell array, at 620.”, paragraph 0040); and
output second data to the plurality of second data pins (“The method 600 may further include selectively routing the first data and the second data to different respective data terminal of the memory package based on a data terminal mapping setting, at 640.”, paragraph 0042)
“to circumvent the swizzle” (paragraph 0015).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhao with Park and Ayyapureddi such that the first data to be sent from the memory device to the storage controller; and
output second data to the plurality of second data pins
“to circumvent the swizzle” (id.).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US 2022/0206695) in view of Bains et al. (US 2015/0095547).
In regards to claim 12, Zhao further teaches that the second data pattern includes a plurality of patterns (Table 1 shows 16 bit sequences),
each of the plurality of patterns includes a same number of bits as a number of the plurality of data lines (Table 1 shows DQ0-DQ15).
Zhao fails to teach one of the same number of bits as the number of the plurality of data lines is a first bit,
bits other than the one of the same number of bits as the number of the plurality of data lines are second bits, and
the second bits are opposite bits of the first bit.
Bains teaches one of the same number of bits as the number of the plurality of data lines is a first bit (“Upon the memory controller 104 receiving (at block 532) the read data on all the HMC data connectors 308a (DQ0-DQ15), the HMC logic 204 determines (at block 534) the HMC data connector receiving the inverted first value, e.g., 1, where all the other HMC data connectors receive the pattern value, e.g., 0.”, paragraph 0028),
bits other than the one of the same number of bits as the number of the plurality of data lines are second bits (“Upon the memory controller 104 receiving (at block 532) the read data on all the HMC data connectors 308a (DQ0-DQ15), the HMC logic 204 determines (at block 534) the HMC data connector receiving the inverted first value, e.g., 1, where all the other HMC data connectors receive the pattern value, e.g., 0.”, paragraph 0028), and
the second bits are opposite bits of the first bit (“Upon the memory controller 104 receiving (at block 532) the read data on all the HMC data connectors 308a (DQ0-DQ15), the HMC logic 204 determines (at block 534) the HMC data connector receiving the inverted first value, e.g., 1, where all the other HMC data connectors receive the pattern value, e.g., 0.”, paragraph 0028)
which “allows the HMC 108 to identify the memory data connector 308b which was masked” (paragraph 0029).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhao with Bains such that one of the same number of bits as the number of the plurality of data lines is a first bit,
bits other than the one of the same number of bits as the number of the plurality of data lines are second bits, and
the second bits are opposite bits of the first bit
which “allows the HMC 108 to identify the memory data connector 308b which was masked” (id.).
In regards to claim 13, Bains further teaches that the number of the plurality of patterns is a same as or one less than the number of the plurality of data lines (“Otherwise, if there are further data memory connectors to map, e.g., DQ(i+1)-DQ15, then i is incremented (at block 542) and control returns to block 508 in FIG. 5a to program the mask mode register bits 202 for the next memory data connector to map.”, paragraph 0028), and
each of the plurality of patterns is different (“The HMC logic 112 sends (at block 508) at least one set command on the HMC command and address connectors 306a to program at least one mask mode register 202 indicating to mask the memory data connector i, where the other memory data connectors other than connector i are not masked.”, paragraph 0024).
In regards to claim 14, Zhao further teaches the third data pattern includes a plurality of patterns (“For example, the host device 350-d may compare a received data pattern (e.g., related to the signaling 630) to a preset or otherwise configured data pattern (e.g., an expected data pattern, expected signaling for one or more information positions).”, paragraph 0123).
Zhao fails to teach that the second data pattern includes a same number of unique identification patterns as a number of the plurality of data lines,
each of the plurality of patterns includes a same number of bits as the number of the plurality of data lines, and
based on the plurality of first data pins sequentially receiving the plurality of patterns, each of the plurality of first data pins receives a pattern corresponding to any one of the unique identification patterns.
Bains teaches that the second data pattern includes a same number of unique identification patterns as a number of the plurality of data lines (“Otherwise, if there are further data memory connectors to map, e.g., DQ(i+1)-DQ15, then i is incremented (at block 542) and control returns to block 508 in FIG. 5a to program the mask mode register bits 202 for the next memory data connector to map.”, paragraph 0028),
each of the plurality of patterns includes a same number of bits as the number of the plurality of data lines (“Upon the memory controller 104 receiving (at block 532) the read data on all the HMC data connectors 308a (DQ0-DQ15), the HMC logic 204 determines (at block 534) the HMC data connector receiving the inverted first value, e.g., 1, where all the other HMC data connectors receive the pattern value, e.g., 0.”, paragraph 0028), and
based on the plurality of first data pins sequentially receiving the plurality of patterns, each of the plurality of first data pins receives a pattern corresponding to any one of the unique identification patterns (“Upon the memory controller 104 receiving (at block 532) the read data on all the HMC data connectors 308a (DQ0-DQ15), the HMC logic 204 determines (at block 534) the HMC data connector receiving the inverted first value, e.g., 1, where all the other HMC data connectors receive the pattern value, e.g., 0. The connector map 400 for the memory 200 is updated (at block 536) to associate the memory data connector i for which mask was programmed in the mask mode registers 202 with the determined HMC data memory connector receiving the inverted mask first value.”, paragraph 0028)
which “allows the HMC 108 to identify the memory data connector 308b which was masked” (paragraph 0029).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhao with Bains such that the second data pattern includes a same number of unique identification patterns as a number of the plurality of data lines,
each of the plurality of patterns includes a same number of bits as the number of the plurality of data lines, and
based on the plurality of first data pins sequentially receiving the plurality of patterns, each of the plurality of first data pins receives a pattern corresponding to any one of the unique identification patterns
which “allows the HMC 108 to identify the memory data connector 308b which was masked” (id.).
In regards to claim 15, Zhao further teaches that the second data pattern is stored in a register of the memory device and sent from the register to the storage controller (“At 630, the memory device 310-d may transmit channel mapping operation signaling based at least in part on the mode register values, or other values. For example, the memory device 310-d may transmit bit sequences, such as those described with reference to Tables 1 and 2, or otherwise convey signaling or pin activations such as those described with reference to FIG. 4B or 5B”, paragraph 0121).
Zhao fails to teach that the command is a read training command. Bains teaches that the command is a read training command (“After sending the command to program the mask mode register to mask the memory data connector i, control proceeds to block 512 in FIG. 5b where the HMC logic 112 sends a read training command to the memory chip 200 to output the data indicated in the pattern and mask mode register bits 202 on the memory data connectors (DQ0-DQ15).”, paragraph 0026) “to ready the memory controller and memory chip for I/O operations” (paragraph 0011). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhao with Bains such that the command is a read training command “to ready the memory controller and memory chip for I/O operations” (id.).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 10 March 2026