Prosecution Insights
Last updated: October 02, 2026
Application No. 18/957,064

CAPACITOR ARRAY

Non-Final OA §102
Filed
Nov 22, 2024
Priority
Jun 06, 2022 — JP 2022-091679 +1 more
Examiner
THOMAS, ERIC W
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
1053 granted / 1276 resolved
+22.5% vs TC avg
Minimal -2% lift
Without
With
+-1.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
1300
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
30.8%
-9.2% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1276 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 7-15, and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Furukawa et al. (US 2021/0082630). PNG media_image1.png 246 492 media_image1.png Greyscale Regarding claim 1, Furukawa et al. disclose in fig. 29B, a capacitor array comprising: a capacitor part including a plurality of capacitor elements (10A, 10B) disposed in a planar arrangement in an in-plane direction orthogonal to a thickness direction (top-bottom), the plurality of capacitor elements (10A, 10B) including mutually adjacent capacitor elements (10A, 10B) that are separated from each other (Fig. 29B), wherein the plurality of capacitor elements (10A, 10B) each include a first electrode layer (21, 22) and a second electrode layer (24) that face each other in the thickness direction (top-bottom) with a dielectric layer (23) interposed between the first electrode layer (21, 22) and the second electrode layer (24); a built-in member (13) disposed at an outer periphery of the capacitor part in the in-plane direction; and a sealing layer (11, 12) that seals the capacitor part (10A, 10B) and the built-in member (13), wherein the built-in member (13A) has a higher melting temperature (glass epoxy resin– [0134]) than the sealing layer (11, 12 - epoxy resin – [0053]). Regarding claim 2, Furukawa et al. disclose the built-in member (13) includes a configuration different from a configuration of each of the plurality of capacitor elements (10A, 10B). Regarding claim 3, Furukawa et al. disclose the built-in member (13) is electrically insulated from the capacitor part (10A, 10B). Regarding claim 4, Furukawa et al. disclose the built-in member (13) is spaced apart from the capacitor part (10A, 10B). Regarding claim 7, Furukawa et al. disclose the built-in member (13) is exposed from the sealing layer (11, 12) in the in-plane direction. Regarding claim 8, Furukawa et al. disclose the built-in member (13) is unexposed from the sealing layer in the thickness direction (only exposed on the length and width ends). Regarding claim 9, Furukawa et al. disclose the built-in member (13) is made of an insulating material (glass epoxy resin– [0134]). Regarding claim 10, Furukawa et al. disclose the first electrode layer (21, 22) is an anode plate (21, 22), the anode plate having: a core made of metal (21 – [0069]), and a porous part (22 – [0070]) on at least one major face of the core (21), wherein the dielectric layer (23, [0072]) is on a surface of the porous part (22), and wherein the second electrode layer (24) is a cathode layer on a surface of the dielectric layer (23). Regarding claim 11, Furukawa et al. disclose the cathode layer includes a solid electrolyte layer (24a, [0074]) on the surface of the dielectric layer (23). Regarding claim 12, Furukawa et al. disclose the built-in member (13) has a height at least equivalent to a thickness of the anode plate (21, 22). Regarding claim 13, Furukawa et al. disclose the built-in member (13) includes a configuration different from a configuration of each of the plurality of capacitor elements (10A, 10B). Regarding claim 14, Furukawa et al. disclose the built-in member (13) is electrically insulated from the capacitor part (10A, 10B). Regarding claim 15, Furukawa et al. disclose the built-in member (13) is spaced apart from the capacitor part (10A, 10B). Regarding claim 18, Furukawa et al. disclose the built-in member (13) is exposed from the sealing layer (11, 12) in the in-plane direction. Regarding claim 19, Furukawa et al. disclose the built-in member (13) is unexposed from the sealing layer in the thickness direction (only exposed on the length and width ends). Allowable Subject Matter Claims 5-6, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: In combination with the other claim limitations, the prior art does not teach or suggest a capacitor array: wherein the built-in member includes a configuration identical to a configuration of each of the plurality of capacitor elements, and is spaced apart and electrically insulated from the capacitor part (claim 5); wherein a width between the built-in member and the capacitor part decreases along the thickness direction (claim 6); wherein the built-in member includes a configuration identical to a configuration of the anode plate, and is spaced apart and electrically insulated from the capacitor part (claim 16); and wherein a width between the built-in member and the capacitor part decreases along the thickness direction (claim 17). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JP H06349680 A – Feed through type capacitor array US 2007/0211414 A1 – Capacitor assembly formed within encapsulation US 2020/0312576 A1 – Capacitor assembly contained within a sealing layer Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC THOMAS whose telephone number is (571)272-1985. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC W THOMAS/Primary Examiner, Art Unit 2847 ERIC THOMAS Primary Examiner Art Unit 2847
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Prosecution Timeline

Nov 22, 2024
Application Filed
Sep 11, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
81%
With Interview (-1.9%)
2y 3m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1276 resolved cases by this examiner. Grant probability derived from career allowance rate.

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