DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 22 November 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12182431. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the limitations of the Patent/Copending Application would anticipate those of the current application as shown in the example claims in the table below.
Instant Application
U.S. Patent No. 12182431
1. A memory system including a storage area divided into a plurality of zones, comprising: a memory device having memory blocks constituting the plurality of zones; a memory controller configured to control write operations of the memory device, wherein the memory controller is configured to: receive a write request and a write pointer associated with a zone from a host; and update a physical pointer when the memory device performs a first write operation in response to the write request received from the host, or when the memory device performs a second write operation in response to an internal write command issued by the memory controller, wherein the physical pointer associated with a physical location where a write operation has been most recently performed in the memory device.
2. The memory system based on claim 1, wherein the second write operation corresponding to the internal write command is a dummy data write operation performed by a flash translation layer of the memory controller.
3. The memory system based on claim 1, wherein the memory controller is configured to, upon receiving the write request from the host, compare the write pointer and the physical pointer of a zone corresponding to the received write request with each other and process the write request based on a result of the comparison.
4. The memory system based on claim 3, wherein, when addresses indicated by the write pointer and the physical pointer match each other, the memory controller is configured to determine whether the write pointer has reached a size of the zone and process the write request based on a result of the determination.
5. The memory system based on claim 4, wherein, when the write pointer has reached the size of the zone, the memory controller is configured to provide, to the host, a message indicating that the zone that is targeted to perform the first write operation corresponding to the write request received from the host is full.
6. The memory system based on claim 4, wherein, when the write pointer has not reached the size of the zone, the memory controller is configured to perform the first write operation corresponding to the write request.
7. The memory system based on claim 3, wherein, when addresses indicated by the write pointer and the physical pointer do not match each other, the memory controller is configured to determine whether the physical pointer has reached a size of the zone and process the write request based on a result of the determination.
8. The memory system based on claim 7, wherein, when the physical pointer has reached the size of the zone, the memory controller is configured to provide, to the host, a message indicating that the zone that is targeted to perform the first write operation corresponding to the write request received from the host is full.
9. The memory system based on claim 7, wherein, when the physical pointer has not reached the size of the zone, the memory controller is configured to perform the first write operation corresponding to the write request.
1. A memory system including a storage area divided into a plurality of zones, comprising:
a memory device having memory blocks constituting the plurality of zones;
a memory controller configured to control write operations of the memory device,
wherein the memory controller is configured to:
receive a write request and a write pointer associated with a zone from a host; and
update a physical pointer when the memory device performs the first write operation in response to the write request received from the host, or when the memory device performs a second write operation in response to an internal write command issued by the memory controller,
wherein the physical pointer indicates a physical location where a write operation has been most recently performed in the memory device.
2. The memory system based on claim 1, wherein the second write operation corresponding to the internal write command is a dummy data write operation performed by a flash translation layer of the memory controller.
3. The memory system based on claim 1, wherein the memory controller is configured to, upon receiving the write request from the host, compare a logical the write pointer and the physical pointer of a zone corresponding to the received write request with each other and process the write request based on a result of the comparison.
4. The memory system based on claim 3, wherein, when addresses indicated by the write pointer and the physical pointer match each other, the memory controller is configured to determine whether the write pointer has reached a size of the zone and process the write request based on a result of the determination.
5. The memory system based on claim 4, wherein, when the write pointer has reached the size of the zone, the memory controller is configured to provide, to the host, a message indicating that the zone that is targeted to perform the first write operation corresponding to the write request received from the host is full.
6. The memory system based on claim 4, wherein, when the write pointer has not reached the size of the zone, the memory controller is configured to perform the first write operation corresponding to the write request.
7. The memory system based on claim 3, wherein, when addresses indicated by the write pointer and the physical pointer do not match each other, the memory controller is configured to determine whether the physical pointer has reached a size of the zone and process the write request based on a result of the determination.
8. The memory system based on claim 7, wherein, when the physical pointer has reached the size of the zone, the memory controller is configured to provide, to the host, a message indicating that the zone that is targeted to perform the first write operation corresponding to the write request received from the host is full.
9. The memory system based on claim 7, wherein, when the physical pointer has not reached the size of the zone, the memory controller is configured to perform the first write operation corresponding to the write request.
A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 13, 14, 17, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Helmick (US 20210334203 A1) in view of Kanno (US 20210223994 A1).
Referring to claims 10 and 17, taking claim 10 as exemplary, Helmick teaches
A memory system, comprising: a memory device having memory blocks constituting a plurality of zones; ([Helmick abstract, 0005-0006] nonvolatile storage unit is divided into a plurality of zones comprising a plurality of erase blocks) a memory controller configured to control operations of the memory device, wherein the memory controller is configured to: ([Helmick abstract, 0005] storage device comprises a controller) receive a data read request for a zone among the plurality of zones, calculate, when a write operation … issued by the memory controller has been performed in the zone, a valid read address based on a first table, ([Helmick abstract, 0005, 0034, 0036, 0045, 0065-0068, Fig. 2A] When a command is received to read data within the NVM, the controller reads the L2P table to determine the LBA and associated pointer of the data. The controller can then determine which zone or erase block the data is stored in, and calculates various offsets of wordlines, pages, and page addresses to find the exact location of the data in the NVM. when searching for a page of a wordline due to a first read command being received, such as to read data stored in the fourth slot 102 of the middle page MP1 324, the controller 108 utilizes the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read. As data is written to a zone 206, a write pointer 210 is advanced or updated to point to or to indicate the next available block in the zone 206 to write data to. After the data associated with the write command has been written to the zone 206, a write pointer 210 is updated to point to the next LBA available for a host write (i.e., the completion point of the first write) and perform a read operation based on the calculated valid read address ([Helmick 0070-0071] the controller 108 utilizes the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read. Since the pointers are consolidated to each zone, a pointer may reference a first or starting physical address of a first zone, a first or starting physical address of a second zone, and so-forth. Thus, each zone would have one pointer that could be utilized to read data in any of the erase blocks of the zone. The controller 108 utilizes the pointer associated with the first zone 350 and incorporates an erase block offset of 1 and the appropriate wordline, page, and slot or NAND location offsets to obtain the target LBA associated with a first read command for the second erase block EB1 300b of the first zone 350. Thus, each zone would have one pointer that could be utilized to read data in any of the erase blocks of the zone.).
Helmick does not explicitly disclose corresponding to an internal write command. Helmick discloses the controller is further configured to write second data associated with one or more second commands sequentially to a second erase block in the first zone, update the first logical to physical address table stored in the volatile memory unit, wherein updating the logical to physical table comprises associating the pointed to the first zone and the second data, and identify a second logical block address of the second data ([Helmick 0087]). Helmick additionally discloses subsequent write commands are 'zone append' commands, Zone management (ZM) commands ([Helmick 0036, 0037, 0044]). A person having ordinary skill in the art would appreciate that these are all internal commands associated to the write process being carried out by the controller.
Kanno teaches corresponding to an internal write command ([Kanno 0157] The flash management unit 20 manages an internal write pointer indicative of a next write location of each zone, similarly to the write pointer of the host 2).
Helmick and Kanno are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Helmick and Kanno before him or her to modify the controller of Helmick to include the internal write commands of Kanno, thereafter the controller is connected to the internal write commands. The suggestion and/or motivation for doing so would be to identify the commands being carried out by the controller as part of the write process as internal write commands. The suggestion and/or motivation for doing so would be that applicant is free to be his or her own lexicographer, see MPEP § 2173.05(a). It is known flash devices and components carry out internal functions including writes to carry out instructions including storage and reading of data. Therefore, it would have been obvious to combine Helmick with Kanno to obtain the invention as specified in the instant application claims.
Referring to claims 13, Helmick in view of Kanno teaches
The memory system based on claim 10, wherein the first table includes information ([Helmick abstract, 0039, 0063, Fig. 4] comprises a logical to physical address (L2P) table for the plurality of zones when searching for a NAND location or a slot due to a first read command being received, such as to read data stored in the fourth slot 102, the controller 108 utilizes the L2P table to find the location of the relevant LBA associated with the physical address of the data to be read) indicating whether data in each page stored in the zone that is targeted to perform the read operation corresponding to the data read request received from a host is user data received from the host or dummy data that fills empty spaces in the zone ([Helmick 0037, 0039] An empty zone switches to an open and active zone once a write is scheduled to the zone or if the zone open command is issued by the host. The data received from the host device with a write command or zone append command may be programmed to an open erase block that is not currently filled with prior data.).
Referring to claim 14, Helmick in view of Kanno teaches
The memory system based on claim 13, wherein the memory controller is configured to calculate the valid read address depending on an offset based on the dummy data included in the first table ([Helmick 0071-0072] The controller 108 utilizes the pointer associated with the first zone 350 and incorporates an erase block offset of 1 and the appropriate wordline, page, and slot or NAND location offsets to obtain the target LBA associated with a first read command for the second erase block EBl 300b of the first zone 350. The data within each zone can be found calculating various offsets.).
Referring to claims 20, Helmick in view of Kanno teaches
The memory controller based on claim 17, comprising: a host interface layer configured to receive the data read request from the host; ([Helmick 0019] storage device 106 may function as a storage device for a host device 104, in accordance with one or more techniques of this disclosure. For instance, the host device 104 may utilize a storage unit 110, such as non-volatile memory, included in storage device 106 to store and retrieve data.) a flash translation layer configured to control the read operation corresponding to the data read request, ([Kanno 0080] The controller 4 may function as a flash translation layer (FTL) configured to execute data management and block management of the NAND flash memory 5.) and a first table including information ([Helmick abstract, 0039, 0063 Fig. 4] comprises a logical to physical address (L2P) table for the plurality of zones) indicating whether data in each page stored in at least one of the plurality of zones is user data received from the host or dummy data that fills empty spaces in the zone ([Helmick 0037, 0039] An empty zone switches to an open and active zone once a write is scheduled to the zone or if the zone open command is issued by the host. The data received from the host device with a write command or zone append command may be programmed to an open erase block that is not currently filled with prior data.).
Allowable Subject Matter
Claims 11-12, 15-16, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the double patenting rejections addressed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132