DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsang (US 2008/0,198,053) in view of Weil (US 2024/0,322,838).
Regarding claim 1 and 11, Tsang disclose an apparatus for digital to analog conversion (DAC 10) comprising:
an inherent first plurality of switch drivers for generating a first pair of control signals and a second pair of control signals (the voltage at the gates of switches is controlled by inherent switch driving circuitry to drive the gate voltages), and
a first plurality of current-steering cells (31, 32, and 33) coupled to the first plurality of switch drivers respectively and a second pair of control signals (Figs. 3-4; paras. [0025]-[0026]),
wherein each of the first plurality of current-steering cells (31, 32, 33) comprises:
a first current source (34) (¶ [0025]);
providing the first pair of control signals to respective control inputs of a first switch pair (M1, M2) coupled between the first current source (34) and a first load (RLOAD+, RLOAD-) of a first cell of a first plurality of current steering cells (31) to generate a first analog signal (Figs. 3, 4; paras. [0025]-[0026]);
and providing the second pair of control signals to respective control inputs of a second switch pair (M3, M4) coupled between the first current source (34) and a second load (RDUMMY+, RDUMMY-) of the first cell of a first plurality of current steering cells (31) to generate a second analog signal, wherein the first switch pair and the second switch pair are coupled to a current source (34) of the first cell (31) providing the first analog signal to the first load circuit (RLOAD+, RLOAD-), and providing the second analog signal to a second load circuit (RDUMMY+, RDUMMY-) (Figs. 3, 4; paras. [0025]-[0026]).
Tsang do not explicitly disclose a first plurality of switch drivers for generating a first pair of control signals and a second pair of control signals, and a first plurality of current steering cells coupled to the first plurality of switch drivers respectively. In the same field of endeavor, Weil disclose a digital to analog converter (DAC 400) comprising a first plurality of switch drivers (408, 410, 412) for generating a first pair of control signals and a second pair of control signals, and a first plurality of current steering cells (402, 406, 404) coupled to the first plurality of switch drivers (408, 410, 412) respectively (Fig. 4; para. [0036]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do so in order to drive the gate voltage of the switches by providing different output drive capacities to match the driver outputs’ timings and reduce timing skew errors (Weil; paras. [0016], [0040]).
Regarding claim 9 and 18, Tsang and Weil disclose the apparatus of claim 1 and 11 respectively, further comprising: an inherent second plurality of switch drivers for generating a third pair of control signals and a fourth pair of control signals; and a second plurality of current-steering cells (32, 33) coupled to the inherent second plurality of switch drivers, respectively, wherein each of the second plurality of current-steering cells (32, 33) comprises: a second current source (34); providing the third pair of control signals to a third switch pair (M1, M2) coupled between the second current source and a third load (RLOAD+, RLOAD-) to generate a third analog signal, providing the third analog signal to a third load circuit (RLOAD+, RLOAD-); and providing the fourth pair of control signals to a fourth switch pair (M3, M4) of the second plurality of current steering cells (32, 33) coupled between the second current source (34) and a fourth load (RDUMMY+, RDUMMY-) to generate a fourth analog signal, and providing the fourth analog signal to a fourth load circuit (RDUMMY+, RDUMMY-) (Tsang, Figs. 3, 4; paras. [0025]-[0026]). Weil disclose a second plurality of current-steering cells (current steering cells 404) coupled to second plurality of switch drivers (switch drivers 412) for generating a third pair of control signals, providing the third pair of control signals to respective control inputs of a third switch pair (460, 462) of a cell of a second plurality of current-steering cells (404) to generate a third analog signal; and providing the fourth pair of control signals to respective control inputs of a fourth switch pair (460, 462) of the cell of the second plurality of current-steering cells (404) to generate a fourth analog signal (paras. [0035]-[0038]; Fig. 4).
Allowable Subject Matter
Claims 2-8, 10, 12-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Tsang and Weil disclose the apparatus of claim 1, wherein the cited prior art fails to further disclose or fairly suggest each of the first plurality of switch drivers includes: a first negated AND (NAND) gate including a first input coupled to a first clock node and a second input coupled to a data node; a second NAND gate including a first input coupled to a second clock node and a second input coupled to the data node; a third NAND gate including a first input coupled to a complementary data node and a second input coupled to the second clock node; and a fourth NAND gate including a first input coupled to the complementary data node and a second input coupled to the first clock node.
Regarding claim 3, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 2, wherein: an output of the first NAND gate is coupled to a control input of a first switch of the first switch pair; an output of the fourth NAND gate is coupled to a control input of a second switch of the first switch pair; an output of the second NAND gate is coupled to a control input of a first switch of the second switch pair; and an output of the third NAND gate is coupled to a control input of a second switch of the second switch pair.
Regarding claim 4, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 2, wherein the first clock node and the second clock node are different nodes.
Regarding claim 5, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 2, further comprising a non-overlapping clock generator including a first output coupled to the first clock node and a second output coupled to the second clock node.
Regarding claim 6, Tsang and Weil disclose the cited prior art fails to further disclose or fairly suggest the apparatus of claim 1, wherein the cited prior art fails to further disclose or fairly suggest the first load comprises a first baseband filter, and the second load comprises a second baseband filter.
Regarding claim 7, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 6, further comprising: a first shunt path coupled between a reference potential node and an input of the first baseband filter; and a second shunt path coupled between the reference potential node and an input of the second baseband filter.
Regarding claim 8, the cited prior art fails to further disclose or fairly suggest the apparatus of claim 6, wherein input signals of the first baseband filter and the second baseband filter comprise return to zero (RZ) signals.
Regarding claim 10, Tsang and Weil disclose the apparatus of claim 9, wherein the cited prior art fails to further disclose or fairly suggest the first switch pair is configured to generate an in-phase (I) analog signal; the second switch pair is configured to generate an I with 45° phase shift (I45) analog signal; the third switch pair is configured to generate a quadrature (Q) analog signal; and the fourth switch pair is configured to generate a Q with 45° phase shift (Q45) analog signal.
Regarding claim 12, Tsang and Weil disclose the method of claim 11, wherein generating the first pair of control signals and the second pair of control signals comprises: performing a first negated AND (NAND) operation based on a first clock signal and a data signal to generate a first control signal of the first pair of control signals; performing a second NAND operation based on a second clock signal and the data signal to generate a first control signal of the second pair of control signals; performing a third NAND operation based on a complementary data signal and the second clock signal to generate a second control signal of the second pair of control signals; and performing a fourth NAND operation based on the complementary data signal and the first clock signal to generate a second control signal of the first pair of control signals.
Regarding claim 13, the cited prior art fails to further disclose or fairly suggest the method of claim 12, wherein the first clock signal and the second clock signal are different clock signals.
Regarding claim 14, the cited prior art fails to further disclose or fairly suggest the method of claim 12, wherein the first clock signal and the second clock signal are non-overlapping clock signals.
Regarding claim 15, Tsang and Weil disclose the method of claim 11, wherein the cited prior art fails to further disclose or fairly suggest the first load circuit comprises a first baseband filter; and the second load circuit comprises a second baseband filter.
Regarding claim 16, the cited prior art fails to further disclose or fairly suggest the method of claim 15, further comprising: coupling an input of the first baseband filter to a reference potential node when generating the second analog signal via the second switch pair; and coupling an input of the second baseband filter to the reference potential node when generating the first analog signal via the first switch pair.
Regarding claim 17, the cited prior art fails to further disclose or fairly suggest the method of claim 15, wherein the first baseband filter and the second baseband filter comprise return-to-zero (RZ) baseband filters
Regarding claim 19, Tsang and Weil disclose the method of claim 18, wherein the cited prior art fails to further disclose or fairly suggest the first analog signal comprises an in-phase (I) analog signal; the second analog signal comprises an I with 45° phase shift (I45) analog signal; the third analog signal comprises a quadrature (Q) analog signal; and the fourth analog signal comprises a Q with 45° phase shift (Q45) analog signal.
Claim 20 is allowed.
Regarding claim 20, Tsang (US 2008/0,198,053) teach a digital to analog converter (DAC 10) comprising: an inherent first plurality of switch drivers (the voltage at the gates of switches is controlled by inherent switch driving circuitry to drive the gate voltages), and
a first plurality of current-steering cells (31, 32, and 33) coupled to the first plurality of switch drivers respectively (Figs. 3-4; paras. [0025]-[0026]), wherein each of the first plurality of current-steering cells (31, 32, 33) comprises: a first current source (34) (¶ [0025]); a first switch pair (M1, M2) coupled between the first current source (34) and a first load (RLOAD+, RLOAD-) (Figs. 3, 4; paras. [0025]-[0026]); and a second switch pair (M3, M4) coupled between the first current source (34) and a second load (RDUMMY+, RDUMMY-) (Figs. 3, 4; paras. [0025]-[0026]).
Weil disclose a transmitter (302) comprising a baseband filter (310) (¶ [0029]), a digital to analog converter (DAC 400) comprising a first plurality of switch drivers (408, 410, 412) and a first plurality of current steering cells (402, 406, 404) coupled to the first plurality of switch drivers (408, 410, 412) respectively (Figs. 3, 4; para. [0036]).
However, the cited prior art fails to further disclose or fairly suggest: a second baseband filter, wherein each of the first plurality of current steering cells comprises: the first switch pair coupled between the first current source and the first baseband filter; and the second switch pair coupled between the first current source and the second baseband filter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
- Saputra et al (US 2022/0,352,899) disclose a digital to analog conversion circuit with a plurality of current steering cells, each current steering cell having a current steering circuit and a switch driver coupled to the current steering circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LANA N LE whose telephone number is (571) 272-7891. The examiner can normally be reached M-F 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley Kim can be reached at (571) 272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LANA N LE/Primary Examiner, Art Unit 2648
Prosecution Insights