DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the Preliminary Amendment filed on 12/17/24. Accordingly, claims 21-40 are currently pending; and claims 1-20 are canceled.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-27, 30, 33 and 34 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 8-16 of U.S. Patent No. 12,192,315.
-Regarding claim 21, claims 1 and 8 of U.S. Patent No. 12,192,315 teaches a monitoring circuit (“monitoring circuit”, col. 16, line 43) comprising:
a phase locked loop “phase locked loop” configured to generate an output signal “output signal “ by dividing an input signal “input signal “ based on a plurality of dividers “plurality of dividers” (see col. 16, lines 44-46); and
a jitter monitoring circuit “jitter monitoring circuit” configured to output a jitter error signal “jitter error signal” based on jitter of a signal generated in the phase locked loop “jitter of a signal“ and a jitter error range “jitter error range” set in a calibration mode “calibration mode” (see col. 16, lines 56-59),
wherein the jitter monitoring circuit comprises: an upper limit jitter monitoring circuit “upper limit jitter monitoring circuit “ configured to set an upper limit level of the jitter error range, and monitor whether the jitter of the signal generated in the phase locked loop is greater than the upper limit level; and a lower limit jitter monitoring circuit “lower limit jitter monitoring circuit” configured to set a lower limit level of the jitter error range, and monitor whether the jitter of the signal generated in the phase locked loop is less than the lower limit level (see col. 17, lines 55-64).
-Regarding claim 22, claim 9 of U.S. Patent No. 12,192,315 encompasses the limitations of the claim.
-Regarding claim 23, claim 10 of U.S. Patent No. 12,192,315 encompasses the limitations of the claim.
-Regarding claim 24, claim 10 of U.S. Patent No. 12,192,315 encompasses the limitations of the claim.
-Regarding claim 25, claim 11 of U.S. Patent No. 12,192,315 encompasses the limitations of the claim, as the claim anticipated by claims 1, 9, 10 and 11 of U.S. Patent No. 12,192,315 .
-Regarding claim 26, as the claim anticipated by claims 1, 9, 10 and 12 of U.S. Patent No. 12,192,315, claim 12 or U.S. Patent No. 12,192,315 teaches that the delay period adjusting circuit comprises an adder “adder” configured to increment a counting number by one based on receiving the comparison result “comparison results” which is activated, from the phase difference detecting circuit in the calibration mode, the activation being indicated by a result that the comparison result has a logic high level “logic high level”, and provide the incremented counting number to the delay circuit.
-Regarding claim 27, claim 13 of U.S. Patent No. 12,192,315 teaches a method of monitoring a phase locked loop “method of monitoring a phase locked loop “ comprising a plurality of dividers “plurality of dividers”, the method comprising:
receiving dividing input signals “dividing input signals” and dividing output signals “dividing output signals” respectively corresponding to the plurality of dividers; and
outputting dividing error signals “dividing error signals” corresponding to respective divider of the plurality of dividers, based on a dividing ratio range’ dividing ratio range” and a dividing ratio “dividing ratio” of the dividing output signal to the dividing input signal corresponding to the respective dividers (see col. 18, lines 41-59).
-Regarding claim 30, claim 14 of U.S. Patent No. 12,192,315 encompasses the limitations of the claim.
-Regarding claim 33, claims 13 and 15 of U.S. Patent No. 12,192,315 teaches the method comprises: outputting a jitter error signal based on jitter of a signal generated in the phase locked loop and a jitter error range set in a calibration mode (see col. 18, lines 51-53), wherein the outputting the jitter error signal comprises: setting an upper limit level and a lower limit level of the jitter error range; and outputting the jitter error signal based on the jitter of the signal generated in the phase locked loop, the upper limit level, and the lower limit level (see col. 19, lines 1-7).
-Regarding claim 34, claim 16 of U.S. Patent No. 12,192,315 encompasses the limitations of the claim.
Allowable Subject Matter
Claims 38-40 are allowed.
Claims 28, 29, 31, 32 and 35-37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
References 2005004649, 10958278, 7627835, 10924125, 10185349 and 20020036545 are additionally cited because they are pertinent to the claimed method(s) and associated system(s).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG M PHU whose telephone number is (571)272-3009. The examiner can normally be reached 8:00-16:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUONG PHU/
Primary Examiner
Art Unit 2632