Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on 04/30/2026 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-13 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,550,586. Although the conflicting claims are not identical, they are not patentably distinct from each other because of the following reasons:
Claims 1-19 of U.S. Patent No. 11,550,586 (hereinafter, “Patent”), contains every element of claims 1-13 of the instant application (hereinafter, “Instant Applicant”) and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
“Claim 12 and Claim 13 are generic to the species of invention covered by claim 3 of the patent. Thus, the generic invention is "anticipated" by the species of the patented invention. Cf., Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (holding that an earlier species disclosure in the prior art defeats any generic claim) 4. This court's predecessor has held that, without a terminal disclaimer, the species claims preclude issuance of the generic application. In re Van Ornum, 686 F.2d 937, 944, 214 USPQ 761, 767 (CCPA 1982); Schneller, 397 F.2d at 354. Accordingly, absent a terminal disclaimer, claims 12 and 13 were properly rejected under the doctrine of obviousness-type double patenting.” (In re Goodman (CA FC) 29 USPQ2d 2010 (12/3/1993).
Patent No.: 11,550,586
Instant Application
1. A method for executing a data transfer operation from a source memory component to a destination memory component comprising: writing, to a control signal register, a control signal representing a custom source access pattern comprising a set of source data blocks in the source memory component, the control signal comprising: a base pointer array address; and an initial destination address; accessing a pointer array at the base pointer array address, the pointer array comprising a set of pointer array elements, each pointer array element: representing a source data block in the set of source data blocks; and comprising: a source address for the source data block; and a source block length for the source data block; writing the initial destination address to a destination address register; and for each pointer array element in the set of pointer array elements: writing the source address for the source data block to a source address register; writing the source block length for the source data block to a source block counter; and in response to a current source block count in the source block counter representing at least one source data word remaining in the source data block: transferring a source data word stored at a current source address in the source address register to a current destination address in the destination address register; incrementing the current source address in the source address register; incrementing the current destination address in the destination address register; and decrementing the current source block count in the source block counter.
1. A method for executing a data transfer operation from a source memory component to a destination memory component, the method comprising: accessing a pointer array comprising a first pointer array element representing a first source data block in the source memory component, the first pointer array element comprising: a first source address for the first source data block; an a first source block length for the first source data block; writing the first source address to a source address register as a current source address; writing the first source block length to a source block counter as a current source block count; transferring a first source data word stored at the current source address in the source address register to a current destination address in a destination address register; incrementing the current source address in the source address register; and decrementing the current source block count in the source block counter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brewerton et al. (US Pub. 2014/0108869).
Regarding independent claims 1 and 10, Brewerton discloses a method for executing a data transfer operation from a source memory component to a destination memory component, the method comprising: accessing a pointer array [a first transaction control set (TCS), as discloses in
paragraph 0010] comprising a first pointer array element representing a first source data block
in the source memory component, the first pointer array element comprising: a first source
address for the first source data block; and a first source block length for the first source data
block [see paragraph 0010, which discloses "a DMA operation can start when the
microprocessor 202 load TCS registers 218 with a first transaction control set (TCS). This first
TCS specifies a source address, destination address, size, and control information for one or
more blocks of data to be transferred within memory 204"]; writing the first source address to a
source address register (source register 220, as discloses in paragraph 0019) as a current
source address; writing the first source block length to a source block counter (count register
224) as a current source block count [see paragraphs 0011 and 0019, particularly paragraph
0019, which discloses "referring to FIG. 3B, to effectuate the desired data transfer, the
processor 302 writes the first transaction control set 320 to the TCS registers 218 in the DMA
controller 306 (see line 334). In particular, the processor 302 writes a base address of the first
data block 308 to source register 220, writes a destination address of a base address of the
first destination block 314 to destination register 222, and writes a size of the first data block
308 to count register 224. The microprocessor also writes control bit(s) to control register 226
to indicate whether the TCS1 320 represents a link that is followed by another transaction
control set"]; transferring a first source data word stored at the current source address in the
source address register to a current destination address in a destination address register
(destination register 222) [see paragraph 0020, which discloses "the DMA controller, acting
through its bus controller 216, then moves or copies first source data block 308 to first
destination block 314 (see line 336). Typically, the DMA moves the data on a word by word
basis, incrementing its count value 224 by one word and incrementing its source and
destination address registers 220, 222 by one word as each word is transferred, until the
specified data size has been transferred. The DMA can compute an actual address error
detection code for the base source and base destination addresses, and stores this actual
address EDC in actual address EDC register 229. The DMA can also compute an actual data
EDC over the transferred data, for example by updating the actual data EDC 231 on a word
by word basis, or by calculating the EDC code on larger chunks of the data"|; incrementing
the current source address in the source address register (see paragraph 0020); and
decrementing the current source block count in the source block counter (see paragraph 0020).
Regarding claim 2, Brewerton discloses "The method of claim 1" [See rejection to claim 1
above], further comprising: accessing a control signal in a control signal register (control
register 226), the control signal comprising an initial destination address; writing the initial
destination address to the destination address register as the current destination address; and
incrementing the current destination address in the destination address register (see paragraphs
0019 and 0020).
Regarding claim 3, Brewerton discloses, further comprising: accessing a control signal in a
control signal register, the control signal comprising: a base pointer array address; and a pointer
array length (see paragraph 0019); and loading the pointer array into a pointer array queue
[location of transaction control set (TCS) registers 218, as disclose in fig. 2 and paragraph
0025] based on the base pointer address and the pointer array length (see paragraph 0025,
which discloses "in this method, a first transaction control set is stored in memory starting at
a first base address. The first transaction control set includes a first source address of first
source data to be transferred and a first destination address where the first source data is to be
transferred. A second transaction control set, which is stored in memory starting at a second
base address that is non-contiguous in memory with the first transaction control set, is also
accessed. The second transaction control set includes a second source address of second
source data to be transferred and a second destination address where the second source data is
to be transferred").
Regarding claim 4, Brewerton discloses, further comprising: reading the first source address
from the first pointer array element in the pointer array queue; reading the first source block
length from the first pointer array element in the pointer array queue; and dequeuing the first
pointer array element from the pointer array queue (see paragraphs 0020 and 0023).
Regarding claim 5, Brewerton discloses, further comprising: writing a base pointer
array address to a pointer address register as a current pointer array address; and for each pointer
array element in a set of pointer array elements in the pointer array: reading a current pointer
array address in the pointer address register; reading a respective source address for a respective
source data block from a respective pointer array element at the current pointer array address;
writing the respective source address to the source address register as the current source address;
reading a respective source block length for the respective source data block from the pointer
array element at the current pointer array address; writing the respective source block length for
the source data block to the source block counter as the current source block count; and
incrementing the current pointer array address in the pointer address register (see paragraphs
0020 and 0025).
Regarding claim 6, Brewerton discloses, wherein transferring the first source data word
stored at the current source address in the source address register to the current destination
address in a destination address register comprises: loading the first source data word from the
current source address into a transpose buffer according to a first buffer dimension of the
transpose buffer; and transferring the first source data word from the transpose buffer according
to a second buffer dimension of the transpose buffer (see paragraph 0015. Note, the claim
language doesn't disclose any specifics about 'dimension').
Regarding claim 7, Brewerton discloses wherein transferring the first source data word
stored at the current source address in the source address register to the current destination
address in a destination address register comprises: loading the first source data word from the
current source address into a data buffer; and transferring the first source data word from the data
buffer to the current destination address (see paragraphs 0015 and 0020).
Regarding claim 8, Brewerton discloses, further comprising: accessing a control signal in a
control signal register, the control signal: representing a source access pattern in the source
memory component, the source access pattern defining a first dimension; and comprising a first
source stride length in the first dimension; and advancing the current source address in the source
address register based on the first source stride length and the current source address (see
paragraphs 0020 and 0021).
Regarding claim 9, Brewerton discloses, further comprising: accessing a control signal in a
control signal register, the control signal: representing a destination storage pattern in the
destination memory component, the destination storage pattern defining a first dimension; and
comprising a first destination stride length in the first dimension; and advancing the current
destination address in the destination address register based on the first destination stride length
and the current destination address (see paragraphs 0019 and 0020).
Regarding claim 11, Brewerton discloses, further comprising: accessing a destination
pointer array comprising a first destination pointer array element representing a first destination
block in a destination memory component, the first destination pointer array element comprising:
a first destination address for the first destination block; and a first destination block length for
the first destination data block; writing the first destination address to a destination address
register as a current destination address; writing the first destination block length to a destination
block counter as a current destination block count; dequeuing the first source data word stored in
the data buffer to the current destination address in the destination address register; incrementing
the current destination address in the destination address register; and decrementing the
destination block count in the destination block counter (see paragraphs 0019, 0020 and 0025).
Regarding claim 12, Brewerton discloses: further comprising accessing a control signal in a
control signal register, the control signal: representing a custom destination storage pattern
comprising the first destination block; and comprising a base destination pointer array address;
and wherein accessing a destination pointer array comprises accessing the destination pointer
array at the base destination pointer array address (see paragraphs 0020 and 0025).
Regarding claim 13, Brewerton discloses: further comprising accessing a control signal in a
control signal register, the control signal: representing a custom source access pattern comprising
the first source data block; and comprising a base source pointer array address; and wherein
accessing a source pointer array comprises accessing the source pointer array at the base source
pointer array address (see paragraphs 0020 and 0025).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Datla et al. (Pub. No.: US 2022/0067536) “PROCESSOR SYSTEM AND METHOD FOR INCREASING DATA-TRANSFER BANDWIDTH DURING EXECUTION OF A SCHEDULED PARALLEL PROCESS”
Considered for teachings related to the field of integrated circuit design and more specifically to a new and useful processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process.
Does not disclose or suggest the first pointer array element comprising: a first source address for the first source data block; an a first source block length for the first source data block; writing the first source address to a source address register as a current source address; writing the first source block length to a source block counter as a current source block count; transferring a first source data word stored at the current source address in the source address register to a current destination address in a destination address register; incrementing the current source address in the source address register; and decrementing the current source block count in the source block counter.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 10:00 am to 6:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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