CTNF 18/957,319 CTNF 87500 DETAILED ACTION Claims 1-24 are presented for examination. The present application is being examined under the AIA (America Invents Act) First Inventor to File. This Office Action is Non-Final . Claims 1, 9 and 17 are independent claims. Claims 2-8, 10-16, 18-24 are dependent claims. This action is responsive to the following communication: corresponding claims filed on 01-21-2025. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-6, 8-14, 16-22, 24 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2022/0405182 (hereinafter, “Siciliani”) in view of U.S. Publication No. 2023/0070958 (hereinafter, “YOU”) . As per claim(s) 1,9,17 1 , Siciliani discloses a method comprising: initiating a boot sequence, at a controller of a memory system, based at least in part on receiving a power signal; (¶ [0046] discloses a processing logic that receives a command to initiate chip initialization from a requestor, such as memory sub-system controller 115 or host system 120, in response to a power-on event. transmitting, from the controller to a memory device of the memory system, a first request for status information; (¶ [0013] discloses how a controller can determine if the previous attempt to initialize the memory device (i.e., a chip initialization operation) has passed or failed by looking at a status register corresponding to the initialization status. receiving, based at least in part on communicating the first request, an indication of an initialization status from the memory device; (¶s [0013]-[0017] discloses an initialization status where the logic value of “0” indicates that the initialization has passed and a logic value is “1” indicates that initialization has failed. ) configuring, by the controller, with the memory device based at least in part on the indication of the initialization status; and (¶s [0013]-[0017] discloses an initialization status where the logic value of “0” indicates that the initialization has passed and a logic value is “1” indicates that initialization has failed.) communicating data between the controller and the memory device using channel interface. (Fig. 2 illustrates a command register or an address register for communicating data between controller 135 or controller 260 with memory devices 204, 216, and 27) Siciliani does not distinctly disclose the following: configuring, by the controller, a channel interface for communicating with the memory device based at least in part on the indication of the initialization status; and communicating data between the controller and the memory device using channel interface based at least in part on configuring the channel interface. However, YOU discloses the following: configuring, by the controller, a channel interface for communicating with the memory device based at least in part on the indication of the initialization status; and (at least ¶s [0031], [0058]-[0059] and [0105] discloses a controller that can be configured to transfer another unit operation of the unit operations to a second memory plane among the plural memory planes based on a status check of a memory plane. Stated differently, the controller is configured to transfer memory operations from one memory to another memory requiring address information. Indeed, “The controller 130 may refer to, or use, the descriptors to determine which channel(s) or way(s) is used to exchange an instruction or data” ) communicating data between the controller and the memory device using channel interface based at least in part on configuring the channel interface. (at least ¶s [0031], [0058]-[0059] and [0105] discloses a controller that can be configured to transfer another unit operation of the unit operations to a second memory plane among the plural memory planes based on a status check of a memory plane. Stated differently, the controller is configured to transfer memory operations from one memory to another memory requiring address information. Indeed, “The controller 130 may refer to, or use, the descriptors to determine which channel(s) or way(s) is used to exchange an instruction or data” ) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Siciliani and YOU because both references are in the same field of endeavor. You’s teaching of configuring memory channels based on status information would enhance Siciliani 's system by expediting data communication, thus enhancing memory operations in a computer system. As per claims 2, 10, 18, Siciliani as modified discloses a method further comprising: receiving, from the memory device, at least one configuration parameter associated with the channel interface based at least in part on the first request for status information. (YOU: The descriptors may include a block or page of parameters describing something about the memory device 150; ¶ [0105] ) As per claims 3, 11, 19, Siciliani as modified discloses a method further comprising: receiving, from the memory device, an indication of one or more of a type, a data rate, or a timing mode associated with the channel interface based at least in part on the first request for status information. (YOU: at least Fig. 6 illustrates a status register that describes the type of status the memory device is in. For example, SR[1] describes the status of the cache program operations. ) As per claims 4, 12, 20, Siciliani as modified discloses a method further comprising: transmitting, from the controller based at least in part on receiving the indication of the initialization status, a second request for state information associated with the channel interface; and receiving one or more state parameters associated with the channel interface based at least in part on transmitting the second request, wherein configuring the channel interface for communicating with the memory device is based at least in part on receiving the one or more state parameters. (YOU: at least Fig. 6 illustrates a status register that describes the type of status the memory device is in. For example, SR[1] describes the status of the cache program operations and ¶ [0105] discloses descriptors that may include a block or page of parameters describing something about the memory device 150. ) As per claims 5, 13, 21, Siciliani as modified discloses a method further comprising wherein the one or more state parameters include one or more of a current interface mode, use of differential signaling, reference voltage (VrefQ) configuration, ZQ calibration status, warmup cycle configuration, duty cycle correction information, or read/write training information. (Fig. 6 illustrates parameter for indicating the operation mode of the memory device. For example, the SR[6] parameter may indicate whether a page program operation, a block erase operation, a cache program operation, a read operation, or a cache read operation are being performed. ) As per claims 6, 14, 22, Siciliani as modified discloses a method further comprising6. The method of claim 1, further comprising: transmitting a third request to the memory device based at least in part on the indication of the initialization status indicating a power loss for the memory device, wherein the third request indicates for the memory device to perform a reset operation. (Siciliani: ¶ [0016] discloses a power-loss event that leads to chip initialization to “reset to the initial values”. ) As per claims 8, 16, 24, Siciliani as modified discloses a method further comprising wherein the power signal received at the controller is a power supply for input/output drivers of the memory device. (receiving an FDh command for chip initialization of at et least component 112; Fig. 1, ¶ [0016] ) 07-21-aia AIA Claim (s) 7, 15, 23 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2022/0405182 (hereinafter, “Siciliani”) in view of U.S. Publication No. 2023/0070958 (hereinafter, “YOU”) and further view of Patent No. 11,934,664 (hereinafter, “Yang”) . As per claims 7, 15, 23, Siciliani as modified discloses a method further comprising wherein the channel interface supports a plurality of timing modes that each include one or more transmission parameters the first request for status information is transmitted using values of the one or more transmission parameters supported by each of the plurality of timing modes. YOU: The descriptors may include a block or page of parameters describing something about the memory device 150; ¶ [0105] Siciliani as modified does not distinctly disclose parameters corresponding to different data communication rates. However, Yang explicitly discloses parameters corresponding to different data communication rates. (a program data rate of the storage device, and a size of data from the host device or the RAID controller to be written to the memory; claim 1) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Siciliani as modified and Yang because all references are in the same field of endeavor. Yang’s teaching of configuring the data rates for memory processing would enhance Siciliani 's as modified system by reducing the amount power needed, thus extending computer operation for longer. Relevant Prior Art Pertinent prior art for the instant application is U.S. Patent No. 12,650,937 by Lee et al. which discloses the invention directed to a memory subsystem is operable with a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. The memory subsystem controller has an open drain output, and is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation. The second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations. The first signaling interface is used by the memory subsystem controller to indicate a parity error in response to a parity error having occurred during the normal operations. The second signaling interface is used by the memory subsystem controller to output a signal related to initialization operation sequences during the initialization operation. Conclusion With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AUREL PRIFTI/Primary Examiner, Art Unit 2175 Aurel Prifti Primary Examiner Art Unit 2175 Tel. (571) 270-1743 Fax (571) 270-2743 aurel.prifti@uspto.gov Application/Control Number: 18/957,319 Page 2 Art Unit: 2175 Application/Control Number: 18/957,319 Page 3 Art Unit: 2175 Application/Control Number: 18/957,319 Page 4 Art Unit: 2175 1 As per independent claim(s) 9, 17, these claims are substantially equivalent to method claim 1, because the additional feature(s) are present on any off the shelf general-purpose computer. Therefore, for at least this reason, claims 9 and 17 also stand rejected. Indeed, at least Fig’s 1-2 of Siciliani further discloses the claimed features by illustrating a system having a processor and a memory for storing instructions.
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