DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aqrabawi et al. (US 20210349519 A1) (herein after Aqrabawi).
Regarding claim 1, Aqrabawi teaches an apparatus comprising: at least one control circuit configured to [Figure 1 & Figure 5 show control circuits (SOC101/SOC2401) that comprises measurement circuitries/sensors (2442/2440), control unit (PCU 2410a/b), control hub (2432), power management circuitries (PMIC 2412) etc.], receive activity information for one or more compute resources; [Figure 5, para 0088:“In an example, PCU 2410 and/or PMIC 2412 may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries 2442, temperature measurement circuitries 2440, charge level of battery 2418, and/or any other appropriate information that may be used for power management.”];
and generate, using a model, based on the activity information, control information to control a power state of at least one of the one or more compute resources [Figure 1, para 0027-0028: “SoC 101 includes power management logic 101a which executes a code 101b (herein referred to as pCode) to manage power for SoC 101 and architecture 100…. Power Management Unit 101a (also referred to as power agent) executes an algorithm using proprietary or OEM (original equipment manufacturer) accessible software code, such as pCode, to analyze these hints and an actual system's number of dirty cache lines to inform the low power state entry decision such as S0i4 vs. S0i3 entry decision. As such, architecture 100 enters a power state that results in higher power savings under the SoC's usage conditions.”].
Regarding claim 2, Aqrabawi teaches the apparatus of claim 1, wherein the at least one control circuit comprises a multiply-accumulate circuit [para 0030: “ML scheme driver 201 comprises or has access to multipliers and adders to train a ML model and generate outputs based on trained weights (or coefficients) and inputs (e.g., telemetry inputs).”].
Regarding claim 3, Aqrabawi teaches the apparatus of claim 1, wherein the at least one control circuit comprises a neural processing unit [para 0030: “In some embodiments, ML scheme driver 201 implements machine-learning using one or more of: Logistic Regression, Random Forest, or Neural Network.”].
Regarding claim 4, Aqrabawi teaches the apparatus of claim 1, wherein the model comprises a neural network [para 0033: “In some embodiment, the ML algorithm uses one or more of: Logistic Regression, Random Forest, or Neural Network to train weights.”].
Regarding claim 5, Aqrabawi teaches the apparatus of claim 1, wherein the activity information comprises first activity information, and the at least one control circuit is further configured to: collect second activity information for the one or more compute resources; and send the second activity information [Figure 2 & 3, para 0032-41: “system telemetry 203 has access to a myriad of user behavior which are used as inputs for ML drivers 201 and 202. In some embodiments, system telemetry 203 logs user ModCS entry and/or exit history and time-in-state (e.g., time spent in a particular power state) in a scratchpad space (e.g., memory) to train the ML algorithm whenever it runs for training….the logs in the scratchpad are events that can be a trigger to start the ML training algorithm by driver 201 (or to start the ML inference algorithm by driver 202)… As ML scheme 201 or 202 runs over time (e.g., throughout a day), it will keep updating the scratch pad with the latest HWM 205. This HWM 205 threshold is regularly compared with a current number of dirty cache lines to predict what power state (e.g., S0i3 or Soi4) to enter…In some embodiments, a change in telemetry information (compared to its previous state or value) is an event that causes ML driver 201 to begin training of its ML model.”];
Regarding claim 6, Aqrabawi teaches the apparatus claim 5, wherein the at least one control circuit is further configured to receive, based on the sending the second activity information, one or more parameters for the model [Figure 3, para 0041: “In some embodiments, a change in telemetry information (compared to its previous state or value) is an event that causes ML driver 201 to begin training of its ML model.”].
Regarding claim 7, Aqrabawi teaches the apparatus of claim 1, wherein the at least one control circuit comprises a buffer to store the activity information [Figure 5, para 0065: “In some embodiments, device 2400 comprises control hub 2432, which represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, processor 2404 may communicate with one or more of display 2422, one or more peripheral devices 2424, storage devices 2428, one or more other external devices 2429, etc., via control hub 2432.”].
Regarding claim 8, Aqrabawi teaches the apparatus of claim 1, The apparatus of claim 1, wherein the at least one control circuit is further configured to generate a timestamp for the activity information [Figure 2, para 0030: “In some embodiments, the architecture to intelligently predict idle time comprises a machine-learning (ML) scheme driver 201 used for training a ML model for dynamic tuning, ML scheme driver 202 used for inference, system telemetry information 203, register to store Time Stamp Counter (TSC) 204, register to store HWM 205, pCode 101b to determine a decision about a lower state, Tag cache 206, and register to store number of dirty lines 207.” Para 0043: “ML driver 201 reads TSC register(s) and updates the TIS register as indicated by block 311.”].
Regarding claim 9, Aqrabawi teaches the apparatus of claim 1, wherein the at least one control circuit is further configured to generate the control information based on a characteristic of at least one of the one or more compute resources [Figure 2, para 0029: “The various blocks may execute in a sequence, in parallel, or out of order to generate the decision to enter a particular power state.”].
Regarding claim 10, Aqrabawi teaches the apparatus of claim 9, wherein the characteristic comprises a breakeven energy [para 0087: “In some embodiments, PCU 2410 and/or PMIC 2412 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit…. As such, voltage and/or frequency can be increased temporality for processor 2404 without violating product reliability.”].
Regarding claim 11, Aqrabawi teaches an apparatus comprising: one or more compute resources configured to: operate in a first power state [Figure 3, para 0042: “At block 305, power management agent 101a compares a current number of dirty lines (cache lines) with the HWM. If the number of dirty lines (DL) is greater than HWM, then power management agent 101a causes SoC 101 or computing system to enter a first power state which is a less deep power state compared to a second power state.”]; and operate, based on control information, in a second power state [para 0043: “ If the number of dirty lines (DL) is less than HWM, then power management agent 101a causes SoC 101 or computing system to enter a second power state which is a more deep power state compared to the first power state.”]; and at least one control circuit configured to: receive activity information for at least one of the one or more compute resources [Figure 5, para 0088:“In an example, PCU 2410 and/or PMIC 2412 may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries 2442, temperature measurement circuitries 2440, charge level of battery 2418, and/or any other appropriate information that may be used for power management.”]; and generate, using a model, based on the activity information, the control information [Figure 2, para 0030: “train a ML model and generate outputs based on trained weights (or coefficients) and inputs (e.g., telemetry inputs). In some embodiments, ML scheme driver 201 implements machine-learning using one or more of: Logistic Regression, Random Forest, or Neural Network.”].
Regarding claim 12, Aqrabawi teaches the apparatus of claim 11, further comprising a power circuit configured to control the second power state based on the control information [para 0043: “If the number of dirty lines (DL) is less than HWM, then power management agent 101a causes SoC 101 or computing system to enter a second power state which is a more deep power state compared to the first power state.”]
Regarding claim 13, Aqrabawi teaches the apparatus of claim 11, wherein the at least one control circuit comprises a multiply-accumulate circuit [para 0030: “ML scheme driver 201 comprises or has access to multipliers and adders to train a ML model and generate outputs based on trained weights (or coefficients) and inputs (e.g., telemetry inputs).”].
Regarding claim 14, Aqrabawi teaches the apparatus of claim 11, wherein the at least one control circuit comprises a neural processing unit [para 0030: “In some embodiments, ML scheme driver 201 implements machine-learning using one or more of: Logistic Regression, Random Forest, or Neural Network.”].
Regarding claim 15, Aqrabawi teaches a method comprising: collecting, using at least one control circuit connected to one or more compute resources, first activity information for the one or more compute resources [Figure 2, para 0032: “system telemetry 203 has access to a myriad of user behavior which are used as inputs for ML drivers 201 and 202”]; training, using the first activity information and a characteristic of at least one of the one or more compute resources, a model [Figure 2, para 0030: “train a ML model and generate outputs based on trained weights (or coefficients) and inputs (e.g., telemetry inputs)]; collecting, using the at least one control circuit, second activity information for the one or more compute resources; generating, using the model and the second activity information, control information; and controlling, using the control information, a power state of at least one of the one or more compute resources [Figure 2 & 3, para 0037-41: “As ML scheme 201 or 202 runs over time (e.g., throughout a day), it will keep updating the scratch pad with the latest HWM 205. This HWM 205 threshold is regularly compared with a current number of dirty cache lines to predict what power state (e.g., S0i3 or Soi4) to enter…In some embodiments, a change in telemetry information (compared to its previous state or value) is an event that causes ML driver 201 to begin training of its ML model.”].
Regarding claim 16, Aqrabawi teaches The method of claim 15, wherein the training comprises: determining, based on the characteristic and a first portion of the first activity information, a first value corresponding to the first portion of the first activity information; determining, based on the characteristic and a second portion of the first activity information, a second value corresponding to the second portion of the first activity information; and generating, using the first portion of the first activity information, the second portion of the first activity information, the first value, and the second value, one or more parameters for the model [Figure 2 & 3, para 0029-41: “The various blocks may execute in a sequence, in parallel, or out of order to generate the decision to enter a particular power state…As ML scheme 201 or 202 runs over time (e.g., throughout a day), it will keep updating the scratch pad with the latest HWM 205. This HWM 205 threshold is regularly compared with a current number of dirty cache lines to predict what power state (e.g., S0i3 or Soi4) to enter…In some embodiments, a change in telemetry information (compared to its previous state or value) is an event that causes ML driver 201 to begin training of its ML model.”].
Examiner’s note: Claim 16 is rejected on broader reasonable interpretation.
Regarding claim 17, Aqrabawi teaches the method of claim 16, wherein the first value comprises a label [para 0037: “As ML scheme 201 or 202 runs over time (e.g., throughout a day), it will keep updating the scratch pad with the latest HWM 205. This HWM 205 threshold is regularly compared with a current number of dirty cache lines to predict what power state (e.g., S0i3 or Soi4) to enter.”].
Examiner’s note: Claim 17 is rejected on broader reasonable interpretation as updating ‘scratch pad’ or ‘HWM 205’ can be interpreted as updating label.
Regarding claim 18, Aqrabawi teaches the method of claim 17, wherein the label comprises information to transition a power state of at least one of the one or more compute resources [para 0037: “This HWM 205 threshold is regularly compared with a current number of dirty cache lines to predict what power state (e.g., S0i3 or Soi4) to enter.”].
Examiner’s note: Claim 18 is rejected on broader reasonable interpretation as ‘HW 205 threshold’ can be interpreted as label that is used to make a transition to different power states.
Regarding claim 19, Aqrabawi teaches the method of claim 16, wherein the first value comprises a quantity [para 0037: “This HWM 205 threshold is regularly compared with a current number of dirty cache lines to predict what power state (e.g., S0i3 or Soi4) to enter.”].
Examiner’s note: Claim 19 is rejected on broader reasonable interpretation as ‘current number of dirty cache lines’ can be interpreted as quantity.
Claim 20 is rejected for the same reason as mentioned in the rejection of claim 10.
Conclusion
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/AFRINA MURSHID/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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