Prosecution Insights
Last updated: October 26, 2026
Application No. 18/957,806

Clock Synchronization Between Access Networks Through Core Network

Non-Final OA §102§103
Filed
Nov 24, 2024
Examiner
LIN, KENNY S
Art Unit
2416
Tech Center
2400 — Computer Networks
Assignee
Cisco Technology Inc.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
623 granted / 885 resolved
+12.4% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
26 currently pending
Career history
914
Total Applications
across all art units

Statute-Specific Performance

§101
7.3%
-32.7% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 885 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-20 are presented for examination. Information Disclosure Statement The IDS filed on 12/18/2024 are considered. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5, 16-17 and 20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dror et a (Dror)l, US 2021/0297230 As per claim 1, Dror teaches the invention including an ingress network device, comprising: A processor (pp. 0024); One or more receive ports (pp. 0021, 0027); One or more transmit ports (pp. 0027); and A memory communicatively coupled to the processor (pp. 0024), wherein the memory comprises a synchronization logic that is configured to: Receive a timing packet at a receive port of the one or more receive ports (pp. 0020, 0027); Capture, in the timing packet, a receive timestamp of receiving the timing packet (pp. 0024, 0027); Add an encapsulation to the timing packet (pp. 0028); and Forward the timing packet via a transmit port of the one or more transmit ports (pp. 0025, 0027, 0038, 0059, 0077). As per claim 2, Dror teaches the invention as claimed in claim 1. Dror further teaches wherein the timing packet comprises a timing value and a correction field (pp. 0025-0027, 0029-0030, 0035-0036). As per claim 3, Dror teaches the invention as claimed in claim 2. Dror further teaches wherein capturing the receive timestamp in the timing packet comprises modifying an existing value of the correction field based on the received timestamp (pp. 0025-0027, 0030). As per claim 4, Dror teaches the invention as claimed in claim 3. Dror further teaches wherein the existing value of the correction field is modified to indicate a difference of the receive timestamp and the existing value of the correction field (pp. 0032). As per claim 5, Dror teaches the invention as claimed in claim 3. Dror further teaches wherein the receive timestamp is captured in the timing packet prior to encapsulating the timing packet (pp. 0027-0028). As per claim 16, Dror teaches the invention including an egress network device, comprising: A processor (pp. 0024); One or more receive ports (pp. 0021, 0027); One or more transmit ports (pp. 0027); and A memory communicatively coupled to the processor (pp. 0024), wherein the memory comprises a synchronization logic that is configured to: Receive an encapsulated timing packet comprising a timing value and a correction field (pp. 0028-0030, 0032); Decapsulate the timing packet (pp. 0032, 0041); Update the correction field based on an existing value of the correction field and a transmit timestamp of the timing packet form the egress network device (pp. 0032-0033, 0035-0036, 0038, 0041); and Forward, at the transmit timestamp, the timing packet with the updated correction field via a transmit port of the one or more transmit ports (pp. 0025, 0027, 0038, 0042, 0059, 0077). As per claim 17, Dror teaches the invention as claimed in claim 16. Dror further teaches wherein the correction field is further updated based on a receive timestamp of the timing packet at an ingress network device (pp. 0020, 0024, 0027, 0032-0033, 0035-0036, 0038, 0041). As per claim 20, Dror teaches the invention including a method for time synchronization, comprising: Receiving a timing packet at a receive port of an ingress network device (pp. 0020, 0027); Capturing, in the timing packet, a receive timestamp of receiving the timing packet (pp. 0024, 0027); Adding an encapsulation to the timing packet (pp. 0028); and Transmitting the timing packet via a transmit port of the ingress network device (pp. 0025, 0027, 0038, 0059, 0077). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6-7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dror et al (Dror), US 2021/0297230, in view of Soo et al (Soo), US 2022/0116373. As per claim 6, Dror teaches the invention as claimed in claim 1. Dror does not teach wherein capturing the receive timestamp in the timing packet comprises assigning metadata to the timing packet, the metadata configured to indicate the receive timestamp. Soo teaches to capture the receive timestamp in the timing packet comprises assigning metadata to the timing packet, the metadata configured to indicate the receive timestamp (pp. 0031, 0047). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Dror and Soo and transmit metadata that includes the timestamp with the timing message. As per claim 7, Dror and Soo teach the invention as claimed in claim 6. Soo further teaches wherein the metadata is further configured to indicate an acceptable threshold range that defines a maximum time difference allowed between the ingress network device and an egress network device (pp. 0033, 0052, 0059). As per claim 19, Dror teaches the invention as claimed in claim 17. Dror does not teach wherein prior to forwarding the timing packet, the synchronization logic is further configured to: Determine a difference between the transmit timestamp and the receive timestamp; Compare the determined difference with an acceptable threshold range; and Permit forwarding of the timing packet based on the determined difference being within the acceptable threshold range. Soo teach to: Determine a difference between the transmit timestamp and the receive timestamp (pp. 0035, 0060); Compare the determined difference with an acceptable threshold range (pp. 0035, 0060); and Permit forwarding of the timing packet based on the determined difference being within the acceptable threshold range (pp. 0036, 0060). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Dror and Soo and manage transmission scheduling and hold off on the transmission of the timing packet if the determined difference of the timestamps is not within an acceptable threshold range. Claim(s) 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dror et al (Dror), US 2021/0297230, in view of McCall et al (McCall), US 2022/0123849. As per claim 15, Dror teaches the invention as claimed in claim 1. Dror does not teach wherein the ingress network device corresponds to an ingress provider edge device in a core network. McCall teaches to implement the ingress network device as an ingress provider edge device in a core network (pp. 0057, 0059, 0133, 0148, 0167). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Dror and McCall to implement the timing synchronization process in edge computing environment. As per claim 18, Dror teaches the invention as claimed in claim 17. Dror does not teach wherein the updated correction field is configured to indicate a timing delay associated with a core network that comprises the egress network device and the ingress network device. McCall teaches to updated correction field is configured to indicate a timing delay associated with a core network that comprises the egress network device and the ingress network device (pp. 0057, 0059, 0133, 0148, 0167). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Dror and McCall to implement the timing synchronization process in edge computing environment and update the correction fields according to the time delays caused by the network communication. Allowable Subject Matter Claims 8-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dror et al, US 2023/0269018 Dror, US 2023/0269161 Kasichainula et al, US 2022/0345417 Zhang, US 2016/0173267 A shortened statutory period for reply to this Office action is set to expire Three MONTHS from the mailing date of this action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNY S LIN whose telephone number is (571) 272-3968. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Noel Beharry can be reached on 571-270-5630. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). KENNY S. LIN Examiner Art Unit 2416 /Kenny S Lin/ Primary Examiner, Art Unit 2416 October 7, 2026
Read full office action

Prosecution Timeline

Nov 24, 2024
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §102, §103
Oct 14, 2026
Examiner Interview Summary
Oct 14, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
82%
With Interview (+11.9%)
2y 11m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 885 resolved cases by this examiner. Grant probability derived from career allowance rate.

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