DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 4 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Panicacci (US 2017/0352696) (cited by the applicant).
Regarding claim 1, Panicacci (Figs. 2, 3A) discloses “an analog-to-digital conversion device (cf. Fig. 2, #209) comprising:
a comparator (cf. Fig. 3A, #318) having a first input terminal (cf. Fig. 3A, '-' input of #318), a second input terminal (cf. Fig. 3A, '+' input of #318), and an output terminal (cf. Fig. 3A, Voutp), and being configured to compare an input signal (cf. Fig. 3A, #316) input through the first input terminal with a reference voltage (cf. Fig. 3A, #308) input through the second input terminal to output a comparison result value (cf. Fig. 3B, Comparator_Voutp) through the output terminal, the reference voltage being decreased by a preset value from a previous value in response to a clock signal (cf. Fig. 3B, Comparator_VIN_P, "At each clock cycle, one or more charge transfer stages 340 may be used to transfer negative charge packets to the floating Cdac1 node 308", §70);
a counter (cf. Fig. 3A, #320) configured to output a digital count value (cf. Fig. 3B, Counter Value) that increases each time the clock signal toggles ("updating the count value stored in the counter comprises: periodically incrementing the count value at the same rate that charges are periodically transferred to the first capacitive node", claim 6);
a register configured to latch the digital count value ("The counter value maintained by the counter 320 may be provided at the output 326 of the counter 320, as an n-bit value in an ADC 300 with an n-bit resolution", §71) based on the comparison result value, and generate a digital value (cf. Fig. 3A, #326) corresponding to the input signal based on the latched digital count value;
a first blocking capacitor (cf. Fig. 3A, #316-2) having a first end (cf. Fig. 3A, right end of #316-2) connected to the first input terminal, and being configured to transmit the input signal to the first input terminal; and
a control circuit (implicitly disclosed; Panicacci discloses "An electronic device with a digital camera module is shown in FIG. 1", §42, which is a self contained system) configured to generate the clock signal”.
Regarding claim 2, Panicacci discloses “the analog-to-digital conversion device of claim 1, further comprising:
a first switch (cf. Fig. 3A, #314-2) connected to the first input terminal, and configured to provide a power supply voltage (cf. Fig. 3A, "the input capacitors 316-1 and 316-2 are clamped (i.e., the clamping switches 314-1 and 314-2 are closed to connect the Vclamp supply voltage terminals to the capacitors 316)", §67) to the first input terminal;
a second switch (cf. Fig. 3A, #314-1) connected to the second input terminal, and configured to provide the power supply voltage (cf. Fig. 3A, "the input capacitors 316-1 and 316-2 are clamped (i.e., the clamping switches 314-1 and 314-2 are closed to connect the Vclamp supply voltage terminals to the capacitors 316)", §67) to the second input terminal”.
Regarding claim 3, Panicacci discloses the analog-to-digital conversion device of claim 2, wherein the control circuit is further configured to generate a switch control signal (clamping switch control signal 714 of Fig. 7A) that controls the first switch (314-1) and the second switch (314-2).
Regarding claim 4, Panicacci discloses the analog-to-digital conversion device of claim 3, wherein the control circuit is further configured to generate the switch control signal to turn the first switch and the second switch on to perform an auto zeroing operation (i.e., the clamping switches 314-1 and 314-2 are closed to connect the Vclamp supply voltage terminals to the capacitors 316)", §67).
Regarding claim 9, Panicacci discloses the analog-to-digital conversion device of claim 1, further comprising a reference generator (340 of Fig. 3A) configured to generate the reference signal (ramp or reference signal 510 of Fig. 5).
Regarding claim 10, Panicacci discloses the analog-to-digital conversion device of claim 9, further comprising a second blocking capacitor (capacitor 316-1 of Fig. 3A) connected between the second input terminal and the reference voltage generator (340), and configured to transmit the reference voltage to the second input terminal.
Regarding claim 11, Panicacci discloses the analog-to-digital conversion device of claim 1, wherein the comparator (318 of Fig. 3A) is further configured to: output, as the comparison result value, a first value when the reference voltage is greater than the input signal; and output, as the comparison result value, a second value different from the first value when the reference voltage is less than the input signal (para. [0077] and [0148]).
Regarding claim 12, Panicacci discloses the analog-to-digital conversion device of claim 11, wherein the register is further configured to latch the digital count value when the comparison result value changes from the first value to the second value ("The counter value maintained by the counter 320 may be provided at the output 326 of the counter 320, as an n-bit value in an ADC 300 with an n-bit resolution", §71).
Allowable Subject Matter
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 13-20 are allowed.
Regarding claims 5-8, Panicacci is not seen to disclose the control circuit that is configured to generate the switch control signal to turn the first switch and the second switch off, and generate an offset detection control signal that controls a preset reference value to be applied as the input signal.
Regarding claims 13-18, Panicacci is not seen to disclose a counter configured to output a digital count value that increases each time the clock signal toggles; a control circuit configured to generate the clock signal; and a plurality of analog-to-digital conversion circuits, wherein each of the plurality of analog-to-digital conversion circuits comprises: a comparator having a first input terminal, a second input terminal, and an output terminal, and being configured to compare an input signal input through the first input terminal with the reference voltage input through the second input terminal to output a comparison result value through the output terminal; a register configured to latch the digital count value based on the comparison result value, and generate a digital value corresponding to the input signal based on the latched digital count value; and a first blocking capacitor having a first end connected to the first input terminal, and being configured to transmit the input signal to the first input terminal. Thus, the claims are allowed.
Regarding claim 19, Panicacci is not seen to disclose the recitation “a plurality of analog-to-digital conversion circuits assigned to the plurality of columns, respectively, and configured to generate, based on the reference voltage, digital values corresponding to pixel signals output through the plurality of columns, wherein each of the plurality of analog-to-digital conversion circuits comprises: a comparator having a first input terminal, a second input terminal, and an output terminal, and being configured to compare a pixel signal input through the first input terminal with the reference voltage input through the second input terminal to output a comparison result value through the output terminal; a register configured to latch the digital count value based on the comparison result value, and generate a digital value corresponding to the pixel signal based on the latched digital count value; and a first blocking capacitor connected to the first input terminal, and configured to transmit the pixel signal to the first input terminal”. Thus, the claim is allowed.
Regarding claim 20, Panicacci is not seen to disclose the claim recitation “a control circuit configured to generate the clock signal; and a plurality of analog-to-digital conversion circuits assigned to the plurality of columns, respectively, and configured to convert analog output signals output through the plurality of columns into digital output signals, each of the analog output signals being generated by physically multiplying each analog input signal corresponding to each of the plurality of rows and corresponding weight information and physically summing multiplication results of all of the plurality of rows for each of the plurality of columns, wherein each of the plurality of analog-to-digital conversion circuits comprises: a comparator having a first input terminal, a second input terminal, and an output terminal, and being configured to compare an analog output signal input through the first input terminal with the reference voltage input through the second input terminal to output a comparison result value through the output terminal; a register configured to latch the digital count value based on the comparison result value, and generate a digital value corresponding to the analog output signal based on the latched digital count value; and a first blocking capacitor connected to the first input terminal, and configured to transmit the analog output signal to the first input terminal”. Thus, the claim is allowed.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon E. Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights