DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-40 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 12/02/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
Current loop of claim 1,
Sampling bridge arms of claim 1,
Signal processing unit of claim 1,
First current loop parameter transmission port of claim 15,
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1, 15 are objected to because of the following informalities:
Claim 1 line 3, “parallel on the” should be –parallel to the--.
Claim 1 line 5, “the number of the current” should be –the number of current--.
Claim 1 line 8, “the current sampling switch” should be –the at least one current sampling switch--.
Claim 1 line 9, “the protection switch” should be –the at least one protection switch--. Similar correction is required in claim 16.
Claim 15 line 29, “S2: acquiring” should be -- S2, acquiring--. Similar correction is required in multiple places.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 and 16-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, line 1 recites “a current loop”. From specification and drawings, it is unclear what forms the loop. For the purpose of examination, the above limitation is interpreted to be a current path and assumed to be the current path comprising protection switch (For example, current path comprising S21 and Ip in fig.2A).
Claim 1 line 14 recites “a high and low state of the load of a current loop”. It is unclear where the load is connected. Specification paragraphs [0013], [0031] do not provide any further information. Further it is unclear what represents high state and low state for a load. For purpose of examination, the above limitation is interpreted as on and off state of protection switch (For example, when S21 is on and when S21 is off in fig.2A).
Claims 2-14 are rejected for the same reasons as stated above for claim 1.
Claims 16-30 are rejected for the same reasons as stated above for claim 1.
Claims 34-40 are rejected for the same reasons as stated above for claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 31-33 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Liu (US 20200220346 A1).
Regarding claim 31, Liu teaches a high-precision current detection integrated chip ([0043], A current imaging principle of the detection field effect transistor), comprising:
a protection switch ([0056], KX MOS transistors) and a current sampling switch ([0056], X MOS switching transistor units);
wherein the first end of the current sampling switch is electrically connected with the first end of the protection switch (e.g. drains are connected, fig.4);
the second end of the current sampling switch is electrically connected with a signal processing unit (e.g. SS1 is connected to protection IC, figs.3-4), and the current sampling switch is configured to obtain a current sampling signal Is by using a mirror current source method ([0066], the current I.sub.SS1k of the sampling circuit is an image current that is obtained by reducing the main circuit current I.sub.S1k by K times);
the signal processing unit is configured to process the current sampling signal Is ([0067], I.sub.S1k is basically equal to a current I.sub.S1) and adjusting the switching states of the current sampling switch and/or the protection switch ([0067], The protection IC determines, based on a value of S.sub.1k, whether to send a turn-off signal to the discharge control terminal G1 and the charge control terminal G2);
the number of the protection switch is one and the number of the current sampling switch is at least two, or, the number of the protection switch is at least two ([0051], where X is an integer greater than or equal to 1, and K is a value greater than 1).
Regarding claim 32, Liu teaches the high-precision current detection integrated chip of claim 31, further comprising: a first protection switch, wherein the first protection switch is reversely connected with the first end of the protection switch in series (e.g. Sb is reversely connected at first end D, fig.4).
Regarding claim 33, Liu teaches the high-precision current detection integrated chip of claim 31, wherein the number of the current sampling switches is two ([0051], where X is an integer greater than or equal to 1);
wherein the second ends of the current sampling switches are respectively connected with the corresponding signal processing unit, or, the second ends of the current sampling switches are connected with the same signal processing unit (e.g. SS1 is connected to protection IC, figs.3-4).
Allowable Subject Matter
Claims 1-30 and 34-40 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, Liu (US 20200220346 A1) teaches a high-precision current detection method ([0043], A current imaging principle of the detection field effect transistor) for current detection in a current loop ([0049], a positive current detection terminal, a negative current detection terminal, a current sampling detection output terminal) with at least one protection switch ([0056], KX MOS transistors), comprising:
arranging sampling bridge arms ([0056], X MOS switching transistor units) which are connected in parallel to the at least one protection switch ([0056], switching transistor group includes (X+KX) switching transistor units that are connected in parallel), wherein each of the sampling bridge arms comprises at least one current sampling switch ([0056], X MOS switching transistor units) and at least one signal processing unit (e.g. protection IC, fig.3) which are connected in series (e.g. SS1 is connected in series to protection IC, figs.3-4); the number of the current sampling switches is at least two, and/or the corresponding protection switches are at least two connected in parallel ([0064], each switching transistor unit of the main circuit part of the switching transistor group includes two switching transistors); the at least one signal processing unit is configured to process a current sampling signal Is ([0067], I.sub.S1k is basically equal to a current I.sub.S1) and configured to adjust the switching states of the current sampling switch and/or the protection switch ([0067], The protection IC determines, based on a value of S.sub.1k, whether to send a turn-off signal to the discharge control terminal G1 and the charge control terminal G2);
obtaining a current sampling signal Is by using a mirror current source method performed by the current sampling switches ([0066], the current I.sub.SS1k of the sampling circuit is an image current that is obtained by reducing the main circuit current I.sub.S1k by K times);
presetting at least one sampling proportion parameter adjustment threshold ([0065], quantity of parallel-connected MOS transistor units);
sampling a first current loop parameter ([0066], [0066] When V.sub.G1SS1k = V.sub.G1S1K, R.sub.DSS1k:R.sub.DS1k is equal to K:1).
Liu does not teach, the first current loop parameter being used for representing a high and low state of the load of a current loop;
determining a magnitude relationship between the first current loop parameter and the sampling proportional parameter adjustment threshold, and adjusting a switching state of the current sampling switch and/or the protection switch according to a determination result;
calculating a current signal Ip according to the current sampling signal Is, and calculating a protection switch current signal Ip by means of a formula (1.1) and a formula (1.2): Q =Rs/Rp （1.1）； Ip = Q·Is （1.2）； wherein Rp is a total equivalent resistance of the protection switch in on state, Rs is a total equivalent resistance of the current sampling switch in on state, and Q is the sampling proportion parameter.
Prior art Hou (US 20210293860 A1), Tonomura (US 20140125289 A1), Matsunaga (US 20050189981 A1) and Jin (CN 106602876 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “the first current loop parameter being used for representing a high and low state of the load of a current loop;
determining a magnitude relationship between the first current loop parameter and the sampling proportional parameter adjustment threshold, and adjusting a switching state of the current sampling switch and/or the protection switch according to a determination result;
calculating a current signal Ip according to the current sampling signal Is, and calculating a protection switch current signal Ip by means of a formula (1.1) and a formula (1.2): Q =Rs/Rp （1.1）； Ip = Q·Is （1.2）； wherein Rp is a total equivalent resistance of the protection switch in on state, Rs is a total equivalent resistance of the current sampling switch in on state, and Q is the sampling proportion parameter.”
Claims 2-14 are allowed, as they depend on allowed claim 1.
Regarding claim 15, Liu (US 20200220346 A1) teaches a step type sampling current decoupling method, adapted to a chip module ([0026], charge management chip).
Liu does not teach, wherein the chip module comprises:
a metering unit, wherein the metering unit is configured to receive a voltage sampling signal Vs obtained by multiplying a current sampling signal Is and a decoupling resistance value, and configured to convert the sampling voltage signal Vs into a metering value of a protection switch current signal Ip according to a sampling proportion parameter Q;
at least one signal processing unit, comprising:
a first current loop parameter transmission port, configured to receive or output a first current loop parameter,
an auxiliary switch unit, electrically connected to the metering unit, wherein the auxiliary switch unit is configured to adjust the decoupling resistance value according to the first current loop parameter, so that a product of the decoupling resistance value and the sampling proportion parameter Q corresponding to the first current loop parameter is a constant value; and
a controller electrically connected to the auxiliary switch unit,
wherein the step type sampling current decoupling method comprises:
S1, setting a corresponding number of auxiliary switch units according to the number n of protection switches, wherein the relationship between the protection switch and the auxiliary switch unit satisfies formula (2):
PNG
media_image1.png
260
423
media_image1.png
Greyscale
wherein Rp1, Rp2……Rpn is total equivalent resistance of the first, the second, and the nth protection switches, R1, R2……Rn is the sampling resistance values of the first, the second, and the nth auxiliary switch units, wherein j is an integer, and 1 < j < n -1;
presetting (n-1) threshold values form the first threshold value to the (n-1)th threshold value which are from small to large;
S2, acquiring the first current loop parameter, and determining a magnitude relationship between the first current loop parameter and the first threshold to the (n-1)th threshold;
S3, if the first current loop parameter is lower than the first threshold, turning-on the first protection switch and all the auxiliary switch units; if the first current loop parameter is higher than the (j-1)th threshold value and is lower than the jth threshold value, turning-on the first to the jth protection switches and the first to (n-j +1)th auxiliary switch units, wherein j is an integer, and 1 < j < n -1; if the first current loop parameter is higher than the (n-1)th threshold, turning on all the protection switches and the first auxiliary switch unit;
S4, taking the total equivalent resistance of the turning-on auxiliary switch unit as a decoupling resistance value, and outputting the voltage value of the two ends of the auxiliary switch unit as a sampling voltage signal Vs.
Prior art Hou (US 20210293860 A1), Tonomura (US 20140125289 A1), Matsunaga (US 20050189981 A1) and Jin (CN 106602876 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the chip module comprises:
a metering unit, wherein the metering unit is configured to receive a voltage sampling signal Vs obtained by multiplying a current sampling signal Is and a decoupling resistance value, and configured to convert the sampling voltage signal Vs into a metering value of a protection switch current signal Ip according to a sampling proportion parameter Q;
at least one signal processing unit, comprising:
a first current loop parameter transmission port, configured to receive or output a first current loop parameter,
an auxiliary switch unit, electrically connected to the metering unit, wherein the auxiliary switch unit is configured to adjust the decoupling resistance value according to the first current loop parameter, so that a product of the decoupling resistance value and the sampling proportion parameter Q corresponding to the first current loop parameter is a constant value; and
a controller electrically connected to the auxiliary switch unit,
wherein the step type sampling current decoupling method comprises:
S1, setting a corresponding number of auxiliary switch units according to the number n of protection switches, wherein the relationship between the protection switch and the auxiliary switch unit satisfies formula (2):
PNG
media_image1.png
260
423
media_image1.png
Greyscale
wherein Rp1, Rp2……Rpn is total equivalent resistance of the first, the second, and the nth protection switches, R1, R2……Rn is the sampling resistance values of the first, the second, and the nth auxiliary switch units, wherein j is an integer, and 1 < j < n -1;
presetting (n-1) threshold values form the first threshold value to the (n-1)th threshold value which are from small to large;
S2, acquiring the first current loop parameter, and determining a magnitude relationship between the first current loop parameter and the first threshold to the (n-1)th threshold;
S3, if the first current loop parameter is lower than the first threshold, turning-on the first protection switch and all the auxiliary switch units; if the first current loop parameter is higher than the (j-1)th threshold value and is lower than the jth threshold value, turning-on the first to the jth protection switches and the first to (n-j +1)th auxiliary switch units, wherein j is an integer, and 1 < j < n -1; if the first current loop parameter is higher than the (n-1)th threshold, turning on all the protection switches and the first auxiliary switch unit;
S4, taking the total equivalent resistance of the turning-on auxiliary switch unit as a decoupling resistance value, and outputting the voltage value of the two ends of the auxiliary switch unit as a sampling voltage signal Vs.”
Regarding claim 16, Liu (US 20200220346 A1) teaches a high-precision current detection unit ([0043], A current imaging principle of the detection field effect transistor) for current detection in a current loop ([0049], a positive current detection terminal, a negative current detection terminal, a current sampling detection output terminal) with at least one protection switch ([0056], KX MOS transistors), comprising:
at least two protection switches ([0056], KX MOS transistors) in parallel ([0056], are connected in parallel), a current sampling switch ([0056], X MOS switching transistor units), a signal processing unit (e.g. protection IC, fig.3);
wherein the first end of the current sampling switch is electrically connected with the first end of the at least one protection switch (e.g. drain D connections, fig.4);
the first input end of the signal processing unit is electrically connected with the second end of the current sampling switch (e.g. SS1 and protection IC are connected, figs.3-4);
the signal processing unit is configured to process a current sampling signal Is ([0067], I.sub.S1k is basically equal to a current I.sub.S1) and configured to adjust the switching states of the current sampling switch and/or the protection switch ([0067], The protection IC determines, based on a value of S.sub.1k, whether to send a turn-off signal to the discharge control terminal G1 and the charge control terminal G2).
Liu does not teach, a first current loop parameter is sampled by the high-precision current unit, the first current loop parameter is being used for representing a high and low state of the load of a current loop; the current sampling signal Is is used to obtain a current signal Ip by means of a formula: Ip = Q·Is; wherein Q is the sampling proportion parameter, and the sampling proportion parameter Q is a ratio of the total equivalent resistance of the conduction sampling switch and the total equivalent resistance of the conduction protection switch.
Prior art Hou (US 20210293860 A1), Tonomura (US 20140125289 A1), Matsunaga (US 20050189981 A1) and Jin (CN 106602876 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “a first current loop parameter is sampled by the high-precision current unit, the first current loop parameter is being used for representing a high and low state of the load of a current loop; the current sampling signal Is is used to obtain a current signal Ip by means of a formula: Ip = Q·Is; wherein Q is the sampling proportion parameter, and the sampling proportion parameter Q is a ratio of the total equivalent resistance of the conduction sampling switch and the total equivalent resistance of the conduction protection switch.”
Claims 17-30 are allowed, as they depend on allowed claim 16.
Regarding claim 34, it is allowed for the same reasons as stated above for claim 1 and claim 15.
Claims 35-40 are allowed, as they depend on allowed claim 34.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 06/03/2026
Prosecution Insights