Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tyminski (US 11,175,691).
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This instant application shows in FIG 1 an integrated circuit with multiple clock signals” as recited in Claim 1 and 15
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Regarding claims 1 and 15, Tyminski (US 11,175,691) discloses a method and an integrated circuit (FIG 1) with multiple clock signals (PLL Clk and XO Clk), comprising: a crystal oscillator circuit (12) configured to generate a first clock signal (XO Clk, 18); a first function circuit (24 and 28) configured to receive the first clock signal and operate according to the first clock signal; a phase-locked loop circuit (20) configured to generate a second clock signal (PLL Clk) according to the first clock signal (18); and a second function circuit configured to receive the second clock signal and operate according (32, 36) to the second clock signal (PLL Clk).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tyminski (US 11,175,691).
Regarding claim 13, Tyminski discloses an integrated circuit with the multiple clock signals except wherein the first function circuit comprises a real time clock circuit. As known in the art, a first function circuit (control module 28) comprising a real time clock circuit is used for real time control and therefore, it would have been obvious to one of ordinary skill in the art to include real time clock circuit in the module 28 because such a modification would have been a mere substitutional art recognized equivalent control module.
Regarding claim 14, Tyminski discloses the integrated circuit with the multiple clock signals except wherein the second function circuit comprises a central processor circuit, a universal serial bus circuit, or an Ethernet circuit. As known in the art, a second function circuit (snapshot module 32 and Rx/Tx 36) comprising a central processor circuit, a universal serial bus circuit, or an Ethernet circuit is used for transmit and receive data and therefore, it would have been obvious to one of ordinary skill in the art to include a central processor circuit, a universal serial bus circuit, or an Ethernet circuit in the module 32 and 36 because such a modification would have been a mere substitutional art recognized equivalent module or Rx/Tx.
Allowable Subject Matter
Claims 2-12 and 16-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the cited references discloses nor suggests the claimed invention including “a reference clock signal generator circuit configured to generate a reference clock signal; a counter circuit configured to generate a counting value according to the first clock signal and the reference clock signal” as set forth in the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu (US 2024/0223193) discloses a PLL with various function modules.
Marutani (US 2011/0074514) discloses PLL synthesizer showing a clock reference generator and various function modules.
Zhang (US 2020/0112315) discloses quick-start clock system with a crystal oscillator and PLL and function modules.
Smith (US 4,670,888) discloses FM modem transmitter showing reference frequency oscillator, PLL and a function module.
Yonekawa (US 5,410,571) discloses PLL showing a reference oscillator and a PLL with a VCO and various function modules.
CN 110166017 disclose a circuit with one IN and two OUTs: a ref CLK, OUT CLK Out 1, LOCK out 2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/Primary Examiner, Art Unit 2849